IDTCSP59910
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
LOW SKEW
PLL CLOCK DRIVER
TURBOCLOCK™ JR.
FEATURES:
•
•
•
•
•
•
Eight zero delay outputs
Selectable positive or negative edge synchronization
Synchronous output enable
Output frequency: 25MHz to 85MHz
TTL outputs
3 skew grades:
CSP59910-2: t
SKEW0
<250ps
CSP59910-5: t
SKEW0
<500ps
CSP59910-7: t
SKEW0
<750ps
3-level input for PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
46mA I
OL
high drive outputs
Low Jitter: <200ps peak-to-peak
Outputs drive 50Ω terminated lines
Pin compatible with Cypress CY7B9910
Available in SOIC Package
IDTCSP59910
DESCRIPTION:
The CSP59910 is a high fanout phase lock loop clock driver in-
tended for high performance computing and data-communications ap-
plications. The CSP59910 has eight zero delay TTL outputs.
The CSP59910 maintains Cypress CY7B9910 compatibility while
providing two additional features: Synchronous Output Enable (GND/
sOE),
and Positive/Negative Edge Synchronization (V
CCQ
/PE). When
the GND/sOE pin is held low, all the outputs are synchronously en-
abled (CY7B9910 compatibility). However, if GND/sOE is held high, all
the outputs except Q2 and Q3 are synchronously disabled.
Furthermore, when the V
CCQ
/PE is held high, all the outputs are
synchronized with the positive edge of the REF clock input (CY7B9910
compatibility). When V
CCQ
/PE is held low, all the outputs are synchro-
nized with the negative edge of REF.
The FB signal is compared with the input REF signal at the phase
detector in order to drive the VCO. Phase differences cause the VCO
of the PLL to adjust upwards or downwards accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
•
•
•
•
•
•
•
•
FUNCTIONAL BLOCK DIAGRAM
V
CCQ
/PE
GND/sOE
Q
0
Q
1
Q
2
Q
3
PLL
REF
Q
4
Q
5
FS
Q
6
Q
7
FB
COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES
1
c
2000
Integrated Device Technology, Inc.
FEBRUARY 2000
DSC-5812/-
IDTCSP59910
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Supply Voltage to Ground
DC Input Voltage
Maximum Power Dissipation (T
A
= 85°C)
T
STG
Storage Temperature Range
Max.
–0.5 to +7
–0.5 to +7
530
(1)
Unit
V
V
mW
REF
V
CC Q
FS
NC
V
CCQ
/PE
V
C CN
Q
0
Q
1
G ND
Q
2
Q
3
V
C CN
1
2
3
4
5
6
7
8
9
10
11
12
SO24-2
24
23
22
21
20
19
18
17
16
15
14
13
G ND
TEST
NC
G ND/sO E
V
CCN
Q
7
Q
6
G ND
Q
5
Q
4
V
CCN
FB
V
I
–65°C to +150°C °C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= 25° C, f = 1MHz, V
IN
= 0V)
Parameter
C
IN
Description
Input Capacitance
Typ. Max.
5
7
Unit
pF
SOIC
TOP VIEW
NOTE:
1. Capacitance applies to all inputs except TEST and FS. It is
characterized but not production tested.
PIN DESCRIPTION
Pin Name
REF
FB
TEST
(1)
GND/
sOE
(1)
V
CCQ
/PE
FS
(2)
Type
IN
IN
IN
IN
IN
IN
Reference Clock Input
Feedback Input
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation.
Synchronous Output Enable. When HIGH, it stops clock outputs (Except Q
2
and Q
3
) in a LOW state - Q
2
and Q
3
may be used as
the feedback signal to maintain phase lock. Set GND/sOE LOW for normal operation.
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the
reference clock.
Frequency range select. 3 level input.
FS = GND: 25 to 35MHz.
FS = MID (or open): 35 to 60MHz
FS = V
CC
: 60 to 85MHz
8 clock output
Power supply for output buffers
Power supply for phase locked loop and other internal circuitry
Ground
Description
Q
0
- Q
7
V
CCN
V
CCQ
GND
OUT
PWR
PWR
PWR
NOTES:
1. When TEST = MID and GND/sOE = HIGH, PLL remains active.
2. This input is wired to Vcc, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL
may require an additional lock time before all data sheet limits are achieved.
2
IDTCSP59910
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RECOMMENDED OPERATING RANGE
CSP59910-5, -7
(Industrial)
Symbol
Vcc
T
A
Description
Power Supply Voltage
Ambient Operating Temperature
Min.
4.5
-40
Max.
5.5
+85
Min.
4.75
0
CSP59910-2
(Commercial)
Max.
5.25
+70
Unit
V
°C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
V
IH
V
IL
V
IHH
V
IMM
V
ILL
I
IN
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
(1)
Input MID Voltage
(1)
Input LOW Voltage
(1)
Input Leakage Current
(REF, FB Inputs Only)
3-Level Input DC Current (TEST, FS)
Input Pull-Up Current (V
CCQ
/PE)
Input Pull-Down Current (GND/sOE)
Output HIGH Voltage
Output LOW Voltage
Output Short Circuit Current
(2)
Conditions
Guaranteed Logic HIGH (REF, FB Inputs Only)
Guaranteed Logic LOW (REF, FB Inputs Only)
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
V
IN
= V
CC
or GND
V
CC
= Max.
V
IN
= V
CC
V
IN
= V
CC
/2
V
IN
= GND
I
PU
I
PD
V
OH
V
OL
I
OS
V
CC
= Max., V
IN
= GND
V
CC
= Max., V
IN
= V
CC
V
CC
= Min., I
OH
=
−16mA
V
CC
= Min., I
OH
=
−40mA
V
CC
= Min., I
OL
= 46mA
V
CC
= Max., V
O
= GND
Min.
2
—
V
CC
−1
V
CC
/2−0.5
—
—
HIGH Level
MID Level
LOW Level
—
—
—
—
—
—
2.4
—
—
Max.
—
0.8
—
V
CC
/2+0.5
1
±5
±200
±50
±200
±100
±100
—
—
0.45
−
250
µA
µA
V
V
V
mA
µA
Unit
V
V
V
V
V
µA
I
3
NOTE:
1. These inputs are normally wired to V
CC
, GND, or unconnected. Internal termination resistors bias unconnected inputs to V
CC
/2. If these inputs are
switched, the function and timing of the outputs may be glitched, and the PLL may require an additional t
LOCK
time before all datasheet limits are
achieved.
2. CSP59910 is to be measured at 25°C with 10:1 duty cycle, one output at a time, and one second maximum.
POWER SUPPLY CHARACTERISTICS
Symbol
I
CCQ
∆I
CC
I
CCD
I
TOT
Parameter
Quiescent Power Supply Current
Power Supply Current per Input HIGH
Dynamic Power Supply Current per Output
Total Power Supply Current
Test Conditions
V
CC
= Max., TEST = MID, REF = LOW,
GND/sOE = LOW, All outputs unloaded
V
CC
= Max., V
IN
= 3.4V
V
CC
= Max., C
L
= 0pF
V
CC
= 5V, F
REF
= 25MHz, C
L
= 240pF
(1)
V
CC
= 5V, F
REF
= 33MHz, C
L
= 240pF
(1)
V
CC
= 5V, F
REF
= 66MHz, C
L
= 240pF
(1)
NOTE:
1. For eight outputs, each loaded with 30pF.
Typ.
10
0.4
100
53
63
117
Max.
40
1.5
160
—
—
—
Unit
mA
mA
µ A/MHz
mA
mA
mA
3
IDTCSP59910
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
INPUT TIMING REQUIREMENTS
Symbol
t
R
, t
F
t
PWC
D
H
R
EF
Description
(1)
Maximum input rise and fall times, 0.8V to 2V
Input clock pulse, HIGH or LOW
Input duty cycle
Reference Clock Input
Min.
—
3
10
25
Max.
10
—
90
85
Unit
ns/V
ns
%
MHz
NOTE:
1. Where pulse width implied by D
H
is less than t
PWC
limit, t
PWC
limit applies.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
CSP59910-2
Symbol
F
REF
Parameter
REF Frequency Range
FS = LOW
FS = MID
FS = HIGH
t
RPWH
t
RPWL
t
SKEW
t
DEV
t
PD
t
ODCV
t
ORISE
t
OFALL
t
LOCK
t
JR
REF Pulse Width HIGH
(1, 7)
REF Pulse Width LOW
(1, 7)
Zero Output Skew (All Outputs)
(1, 3)
Device-to-Device Skew
( 1,2, 4)
REF Input to FB Propagation Delay
( 1,6)
Output Duty Cycle Variation from 50%
(1)
Output Rise Time
(1)
Output Fall Time
(1)
PLL Lock Time
(5)
Cycle-to-Cycle Output Jitter
RMS
Peak-to-Peak
Min.
25
35
60
3
3
—
—
−0.25
−1.2
0.15
0.15
—
—
—
Typ.
—
—
—
—
—
0.1
—
0
0
1
1
—
—
—
Max.
35
60
85
—
—
0.25
0.75
0.25
1.2
1.5
1.5
0.5
25
200
Min.
25
35
60
3
3
—
—
−0.5
−1.2
0.15
0.15
—
—
—
CSP59910-5
Typ.
—
—
—
—
—
0.25
—
0
0
1
1
—
—
—
Max.
35
60
85
—
—
0.5
1.25
0.5
1.2
1.5
1.5
0.5
25
200
Min.
25
35
60
3
3
—
—
−0.7
−1.2
0.15
0.15
—
—
—
CSP59910-7
Typ.
—
—
—
—
—
0.3
—
0
0
1.5
1.5
—
—
—
Max.
35
60
85
—
—
0.75
1.65
0.7
1.2
2.5
2.5
0.5
25
200
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
Unit
MHz
NOTES:
1. All timing tolerances apply for F
NOM
≥25MHz.
2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load.
3. t
SKEW
is the skew between all outputs. See AC test loads.
4. t
DEV
is the output-to-output skew between any two devices operating under the same conditions (V
CC
, ambient temperature, air flow, etc.)
5. t
LOCK
is the time that is required before synchronization is achieved. This specification is valid only after V
CC
is stable and within normal operating
limits. This parameter is measured from the application of a new signal or frequency at REF or FB until t
PD
is within specified limits.
6. t
PD
is measured with REF input rise and fall times (from 0.8V to 2.0V) of 1.0ns.
7. Refer to Input Timing Requirements for more detail.
4
IDTCSP59910
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC TEST LOADS AND WAVEFORMS
V
CC
3.0V
2.0V
Vth = 1.5V
≤
1ns
≤
1ns
130
Ω
Outpu t
0.8V
0V
TTL INPUT TEST WAVEFORM
91
Ω
C
L
C
L
= 50pF (C
L
= 30pF for -2 and -5 device s)
t
O R IS E
t
OF AL L
TEST LOAD
2.0V
0.8V
TTL OUTPUT WAVEFORM
AC TIMING DIAGRAM
t
R EF
t
RP W H
REF
t
RP W L
t
PD
t
OD C V
t
OD C V
FB
t
JR
Q
t
SK E W
t
S K EW
OTHER Q
NOTES:
Skew: The time between the earliest and the latest output transition among all outputs when all are loaded with 50pF (30pF for -2 and -5)
and terminated with 50Ω to 2.06V.
t
SKEW
: The skew between all outputs.
t
DEV
:
The output-to-output skew between any two devices operating under the same conditions (V
CC
, ambient temperature, air flow,
etc.)
t
ODCV
: The deviation of the output from a 50% duty cycle.
t
ORISE
and t
OFALL
are measured between 0.8V and 2V.
t
LOCK
:
The time that is required before synchronization is achieved. This specification is valid only after V
CC
is stable and within normal
operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until t
PD
is within
specified limits.
5
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