2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
FLASH MEMORY
MT28F002B5
MT28F200B5
5V Only, Dual Supply (Smart 5)
40-Pin TSOP Type I 48-Pin TSOP Type I
FEATURES
• Five erase blocks:
16KB/8K-word boot block (protected)
Two 8KB/4K-word parameter blocks
Two main memory blocks
• Smart 5 technology (B5):
5V
±10%
V
CC
5V
±10%
V
PP
application/production
programming
12V
±5%
V
PP
compatibility production
programming
• Address access times: 60ns, 80ns
• 100,000 ERASE cycles
• Industry-standard pinouts
• Inputs and outputs are fully TTL-compatible
• Automated write and erase algorithm
• Two-cycle WRITE/ERASE sequence
• Byte- or word-wide READ and WRITE
(MT28F200B5, 128K x 16/256K x 8)
• Byte-wide READ and WRITE only
(MT28F002B5, 256K x 8)
• TSOP and SOP packaging options
44-Pin SOP
GENERAL DESCRIPTION
The MT28F002B5 (x8) and MT28F200B5 (x16/x8)
are nonvolatile, electrically block-erasable (flash), pro-
grammable, read-only memories containing 2,097,152
bits organized as 262,144 bytes (8 bits) or 131,072
words (16 bits). Writing or erasing the device is done
with a 5V V
PP
voltage, while all operations are per-
formed with a 5V V
CC
. Due to process technology
advances, 5V V
PP
is optimal for application and produc-
tion programming. For backward compatibility with
SmartVoltage technology, 12V V
PP
is supported for a
maximum of 100 cycles and may be connected for up
to 100 cumulative hours. These devices are fabricated
with Micron’s advanced CMOS floating-gate process.
The MT28F002B5 and MT28F200B5 are organized
into five separately erasable blocks. To ensure that
critical firmware is protected from accidental erasure or
overwrite, the devices feature a hardware-protected
boot block. Writing or erasing the boot block requires
either applying a super-voltage to the RP# pin or driv-
ing WP# HIGH in addition to executing the normal
write or erase sequences. This block may be used to store
code implemented in low-level system recovery. The
remaining blocks vary in density and are written and
erased with no additional security measures.
Please refer to
Micron’s Web site
(www.micron.com/
flash/htmls/datasheets.html)
for the latest data sheet.
OPTIONS
• Timing
60ns access
80ns access
80ns access
• Configurations
256K x 8
128K x 16/256K x 8
• Boot Block Starting Word Address
Top (1FFFFH)
Bottom (00000H)
• Operating Temperature Range
Commercial (0°C to +70°C)
Extended (-40°C to +85°C)
• Packages
Plastic 44-pin SOP (600 mil)
Plastic 48-pin TSOP Type 1
(12mm x 20mm)
Plastic 40-pin TSOP
(10mm x 20mm)
Part Number Example:
MARKING
-6
-8
-8 ET
MT28F002B5
MT28F200B5
T
B
None
ET
SG
WG
VG
MT28F200B5SG-8 T
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
PIN ASSIGNMENT (Top View)
48-Pin TSOP Type I
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RP#
V
PP
WP#
NC
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
V
SS
DQ15/(A - 1)
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
V
PP
WP#
NC
A7
A6
A5
A4
A3
A2
A1
A0
CE#
V
SS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44-Pin SOP
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RP#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V
SS
DQ15/(A - 1)
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
ORDER NUMBER AND PART MARKING
MT28F200B5WG-6 B
MT28F200B5WG-6 T
MT28F200B5WG-8 B
MT28F200B5WG-8 T
MT28F200B5WG-8 BET
MT28F200B5WG-8 TET
DQ3
DQ11
ORDER NUMBER AND PART MARKING
MT28F200B5SG-6 B
MT28F200B5SG-6 T
MT28F200B5SG-8 B
MT28F200B5SG-8 T
MT28F200B5SG-8 BET
MT28F200B5SG-8 TET
40-Pin TSOP Type I
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RP#
V
PP
WP#
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
V
SS
NC
NC
A10
DQ7
DQ6
DQ5
DQ4
V
CC
V
CC
NC
DQ3
DQ2
DQ1
DQ0
OE#
V
SS
CE#
A0
ORDER NUMBER AND PART MARKING
MT28F002B5VG-6 B
MT28F002B5VG-6 T
MT28F002B5VG-8 B
MT28F002B5VG-8 T
MT28F002B5VG-8 BET
MT28F002B5VG-8 TET
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
FUNCTIONAL BLOCK DIAGRAM
8
Input
Buffer
BYTE#
1
I/O
Control
Logic
7
16KB Boot Block
18 (19)
9
9
(10)
Input
Buffer
Addr.
A0-A16/(A17)
A9
Buffer/
Latch
8KB Parameter Block
8KB Parameter Block
96KB Main Block
Input
Buffer
(A - 1)
Input Data
Latch/Mux
128KB Main Block
16
X - Decoder/Block Erase Control
Addr.
Power
(Current)
Control
Counter
DQ15/(A - 1)
1
DQ8-DQ14
1
WP#
CE#
OE#
WE#
RP#
V
CC
V
PP
V
PP
Switch/
Pump
Command
Execution
Logic
State
Machine
Y-
Decoder
7
Y - Select Gates
8
Sense Amplifiers
Write/Erase-Bit
Compare and Verify
DQ0-DQ7
Output
Buffer
DQ15
Status
Register
Identification
Register
7
Output
Buffer
8
Output
Buffer
MUX
8
NOTE
1. Does not apply to MT28F002B5.
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
PIN DESCRIPTIONS
44-PIN SOP 40-PIN TSOP 48-PIN TSOP
NUMBERS NUMBERS NUMBERS SYMBOL
43
9
11
WE#
TYPE
Input
DESCRIPTION
Write Enable: Determines if a given cycle is a WRITE cycle. If
WE# is LOW, the cycle is either a WRITE to the command
execution logic (CEL) or to the memory array.
Write Protect: Unlocks the boot block when HIGH if V
PP
=
V
PPH
1
(5V) or V
PPH
2
(12V)
1
and RP# = V
IH
during a WRITE or
ERASE. Does not affect WRITE or ERASE operation on other
blocks.
Chip Enable: Activates the device when LOW. When CE# is
HIGH, the device is disabled and goes into standby power
mode.
Reset/Power-Down: When LOW, RP# clears the status register,
sets the internal state machine (ISM) to the array read mode
and places the device in deep power-down mode. All inputs,
including CE#, are “Don’t Care,” and all outputs are High-Z.
RP# unlocks the boot block and overrides the condition of
WP# when at V
HH
(12V), and must be held at V
IH
during all
other modes of operation.
Output Enable: Enables data output buffers when LOW.
When OE# is HIGH, the output buffers are disabled.
Byte Enable: If BYTE# = HIGH, the upper byte is active through
DQ8-DQ15. If BYTE# = LOW, DQ8-DQ14 are High-Z, and all
data is accessed through DQ0-DQ7. DQ15/(A - 1) becomes the
least significant address input.
Address Inputs: Select a unique, 16-bit word or 8-bit byte. The
DQ15/(A - 1) input becomes the lowest order address when
BYTE# = LOW (MT28F200B5) to allow for a selection of an
8-bit byte from the 262,144 available.
2
12
14
WP#
Input
12
22
26
CE#
Input
44
10
12
RP#
Input
14
33
24
–
28
47
OE#
BYTE#
Input
Input
11, 10, 9, 8, 21, 20, 19,
25, 24, 23,
7, 6, 5, 4,
18, 17, 16,
22, 21, 20,
42, 41, 40, 15, 14, 8, 7, 19, 18, 8, 7,
39, 38, 37, 36, 6, 5, 4, 3, 6, 5, 4, 3, 2,
36, 35, 34
2, 1, 40
1, 48
31
–
45
A0-A16/
(A17)
Input
15, 17, 19,
21, 24, 26,
28, 30
16, 18, 20,
22, 25, 27,
29
1
23
13, 32
3
Input/ Data I/O: MSB of data when BYTE# = HIGH. Address Input: LSB
Output of address input when BYTE# = LOW during READ or WRITE
operation.
25-28, 32-35 29, 31, 33, DQ0-DQ7
Input/ Data I/Os: Data output pins during any READ operation or
35, 38, 40,
Output data input pins during a WRITE. These pins are used to input
42, 44
commands to the CEL.
–
30, 32, 34, DQ8-DQ14
Input/ Data I/Os: Data output pins during any READ operation or
36, 39, 41,
Output data input pins during a WRITE when BYTE# = HIGH. These
43
pins are High-Z when BYTE# is LOW.
11
13
V
PP
Supply Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM
until completion of the WRITE or ERASE, V
PP
must be at V
PPH
1
(5V) or V
PPH
2
(12V)
1
. V
PP
= “Don’t Care” during all other
operations.
30, 31
37
V
CC
Supply Power Supply: +5V
±10%.
23, 39
27, 46
V
SS
Supply Ground.
13, 29, 37, 38 9, 10, 15-17
NC
–
No Connect: These pins may be driven or left unconnected.
DQ15
(A - 1)
NOTE:
1. For SmartVoltage-compatible production programming, 12V V
PP
is supported for a maximum of 100 cycles and may
be connected for up to 100 cumulative hours.
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
2Mb
SMART 5 BOOT BLOCK FLASH MEMORY
TRUTH TABLE (MT28F200B5)
1
FUNCTION
Standby
RESET
READ
READ (word mode)
READ (byte mode)
Output Disable
WRITE/ERASE (EXCEPT BOOT BLOCK)
2
ERASE SETUP
ERASE CONFIRM
3
WRITE SETUP
WRITE (word mode)
4
WRITE (byte mode)
4
READ ARRAY
5
WRITE/ERASE (BOOT BLOCK)
2, 7
ERASE SETUP
ERASE CONFIRM
3
ERASE CONFIRM
3, 6
WRITE SETUP
WRITE (word mode)
4
WRITE (word mode)
4, 6
WRITE (byte mode)
4
WRITE (byte mode)
4, 6
READ ARRAY
5
DEVICE IDENTIFICATION
8, 9
Manufacturer Compatibility
(word mode)
10
Manufacturer Compatibility
(byte mode)
Device (word mode, top boot)
10
Device (byte mode, top boot)
Device (word mode, bottom boot)
10
Device (byte mode, bottom boot)
NOTE:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
RP#
H
L
H
H
H
H
H
H
H
H
H
H
V
HH
H
H
V
HH
H
V
HH
H
H
H
H
H
H
H
H
CE#
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
OE#
X
X
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
WE# WP# BYTE# A0
X
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
H
X
H
X
X
X
X
X
X
X
X
X
H
L
X
X
X
X
H
L
X
X
X
X
X
H
H
L
L
X
H
L
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
H
H
H
A9
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
ID
V
ID
V
ID
V
ID
V
ID
V
ID
V
PP
X
X
X
X
X
X
V
PPH
X
V
PPH
V
PPH
X
X
V
PPH
V
PPH
X
V
PPH
V
PPH
V
PPH
V
PPH
X
X
X
X
X
X
X
DQ0-DQ7 DQ8-DQ14 DQ15/A - 1
High-Z
High-Z
Data-Out
Data-Out
High-Z
20H
D0H
10H/40H
Data-In
Data-In
FFH
20H
D0H
D0H
10H/40H
Data-In
Data-In
Data-In
Data-In
FFH
89H
89H
74H
74H
75H
75H
High-Z
High-Z
Data-Out
High-Z
High-Z
X
X
X
Data-In
X
X
X
X
X
X
Data-In
Data-In
X
X
X
00H
High-Z
22H
High-Z
22H
High-Z
High-Z
High-Z
Data-Out
A-1
High-Z
X
X
X
Data-In
A-1
X
X
X
X
X
Data-In
Data-In
A-1
A-1
X
–
X
–
X
–
X
L = V
IL
(LOW), H = V
IH
(HIGH), X = V
IL
or V
IH
(“Don’t Care”).
V
PPH
= V
PPH1
= 5V.
Operation must be preceded by ERASE SETUP command.
Operation must be preceded by WRITE SETUP command.
The READ ARRAY command must be issued before reading the array after writing or erasing.
When WP# = V
IH
, RP# may be at V
IH
or V
HH
.
V
HH
= 12V.
V
ID
= 12V; may also be read by issuing the IDENTIFY DEVICE command.
A1-A8, A10-A16 = V
IL
.
Value reflects DQ8-DQ15.
2Mb Smart 5 Boot Block Flash Memory
F50.p65 – Rev. 1/00
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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