ADVANCE
‡
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V V
DD
, HSTL, DDR SIO SRAM
36Mb DDR SIO SRAM
2-WORD BURST
Features
•
•
•
•
•
•
•
•
•
DLL circuitry for accurate output data placement
Separate independent read and write data ports
DDR READ or WRITE operation initiated each cycle
Fast clock to valid data times
Full data coherency, providing most current data
Two-tick burst counter for low DDR transaction size
Double data rate operation on read and write ports
Two input clocks (K and K#) for precise DDR timing at
clock rising edges only
Two output clocks (C and C#) for precise flight time
and clock skew matching—clock and data delivered
together to receiving device
Optional-use echo clocks (CQ and CQ#) for flexible
receive data synchronization
Single address bus
Simple control logic for easy depth expansion
Internally self-timed, registered writes
Core V
DD
= 1.8V (±0.1V); I/O V
DD
Q = 1.5V to V
DD
(±0.1V) HSTL
Clock-stop capability with µs restart
15mm x 17mm, 1mm pitch, 11 x 15 grid FBGA package
User-programmable impedance output
JTAG boundary scan
MT57W4MH8C
MT57W4MH9C
MT57W2MH18C
MT57W1MH36C
Figure 1: 165-Ball FBGA
•
•
•
•
•
•
•
•
Table 1:
Valid Part Numbers
DESCRIPTION
4 Meg x 8, DDR SIOb2 FBGA
4 Meg x 9, DDR SIOb2 FBGA
2 Meg x 18, DDR SIOb2 FBGA
1Meg x 36, DDR SIOb2 FBGA
PART NUMBER
MT57W4MH8CF-xx
MT57W4MH9CF-xx
MT57W2MH18CF-xx
MT57W1MH36CF-xx
•
Options
• Clock Cycle Timing
3ns (333 MHz)
3.3ns (300 MHz)
4ns (250 MHz)
5ns (200 MHz)
6ns (167 MHz)
7.5ns (133 MHz)
• Configurations
4 Meg x 8
4 Meg x 9
1 Meg x 18
1 Meg x 36
• Package
165-ball, 15mm x 17mm FBGA
NOTE:
Marking
1
-3
-3.3
-4
-5
-6
-7.5
MT57W4MH8C
MT57W4MH9C
MT57W2MH18C
MT57W1MH36C
F
General Description
1. A Part Marking Guide for the FBGA devices can be found on
Micron’s Web site—http://www.micron.com/numberguide.
The Micron
®
DDR separate I/O, synchronous, pipe-
lined burst SRAM employs high-speed, low-power
CMOS designs using an advanced 6T CMOS process.
The DDR architecture consists of two separate DDR
(double data rate) ports to access the memory array.
The read port has dedicated data outputs to support
READ operations. The write port has dedicated data
inputs to support WRITE operations. This architecture
eliminates the need for high-speed bus turnaround.
Access to each port is accomplished using a common
address bus. Addresses for reads and writes are latched
on the rising edge of the K input clock. Each address
location is associated with two words that burst
sequentially into or out of the device. Bus turnaround
cycles are eliminated and a new data transaction can
be requested each clock cycle, permitting higher
request rates than DDR SRAMs without separated
input and output buses.
36Mb: 1.8V V
DD
, HSTL, QDRB2 SRAM
MT57W2MH18C_B.fm – Rev. B, Pub. 2/03
1
©2003 Micron Technology, Inc.
‡
PRODUCTS
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V V
DD
, HSTL, DDR SIO SRAM
Depth expansion is accomplished with a single
device select (LD#), which is received at K rising edge.
All synchronous inputs pass through registers con-
trolled by the K or K# input clock rising edges. Active
low byte writes (BWx#) permit byte or nibble write
selection. Write data and byte writes are registered on
the rising edges of both K and K#. The addressing
within each burst of two is fixed and sequential, begin-
ning with the lowest address and ending with the high-
est address. All synchronous data outputs pass
through output registers controlled by the rising edges
of the output clocks (C and C# if provided, otherwise K
and K#)
.
Four balls are used to implement JTAG test capabili-
ties: test mode select (TMS), test data-in (TDI), test
clock (TCK), and test data-out (TDO). JTAG circuitry is
used to serially shift data to and from the SRAM. JTAG
inputs use JEDEC-standard 1.8V I/O levels to shift data
during this testing mode of operation.
The SRAM operates from a 1.8V power supply, and
all inputs and outputs are HSTL-compatible. The
device is ideally suited for applications that require a
new transaction to be initiated each clock cycle.
Please refer to Micron’s Web site (www.micron.com/
sramds)
for the latest data sheet.
READ cycles are pipelined. The request is initiated
by driving R/W# HIGH and providing the address at K
rising edge. Data is delivered after the rising edge of K#
(t + 1) using C and C# as the output timing references
or using K and K# if C and C# are tied HIGH. If C and
C# are tied HIGH, they may not be toggled during
device operation. Output tri-stating is automatically
controlled such that the bus is released if no data is
being delivered. This permits banked SRAM systems
with no complex OE timing generation. Back-to-back
READ cycles can be initiated every K rising edge.
WRITE cycles are initiated by driving R/W# LOW
and provide the address at K rising edge. Data is
expected at the rising edge of K and K#, beginning at
the next K rising edge after the cycle is initiated. Write
registers are incorporated to facilitate pipelined self-
timed WRITE cycles and to provide fully coherent data
for all combinations of reads and writes. A read can
immediately follow a write even if they are to the same
address. Although the write data has not been written
to the memory array, the SRAM will deliver the data
from the write register instead of using the older data
from the memory array. The latest data is always uti-
lized for all bus transactions. WRITE cycles can be ini-
tiated on every K rising edge.
READ/WRITE Operations
All bus transactions operate on an uninterruptable
burst of two data, requiring one full clock cycle of bus
utilization. Any transaction type can be initiated at K
rising edge independent of the previous transaction
type. This permits any random operation without ever
needing bus turnaround delays.
Partial WRITE Operations
BYTE WRITE operations are supported, except for
x8 devices in which nibble write is supported. The
active LOW write controls, BWx# (NWx#), are regis-
tered coincident with their corresponding data. This
feature can eliminate the need for some READ-MOD-
IFY-WRITE cycles, collapsing it to a single BYTE/NIB-
BLE WRITE operation in some instances.
36Mb: 1.8V V
DD
, HSTL, QDRB2 SRAM
MT57W2MH18C_B.fm – Rev. B, Pub. 2/03
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V V
DD
, HSTL, DDR SIO SRAM
Programmable Impedance Output
Buffer
The DDR SRAM is equipped with programmable
impedance output buffers. This allows a user to match
the driver impedance to the system. To adjust the
impedance, an external precision resistor (RQ) is con-
nected between the ZQ ball and V
SS
. The value of the
resistor must be five times the desired impedance. For
example, a 350
W
resistor is required for an output
impedance of 70
W
. To ensure that output impedance
is one-fifth the value of RQ (within 15 percent), the
range of RQ is 175
W
to 350
W
. Alternately, the ZQ ball
can be connected directly to V
DD
Q, which will place
the device in a minimum impedance mode.
Output impedance updates may be required
because variations may occur over time in supply volt-
age and temperature. The device samples the value of
RQ. Impedance updates are transparent to the system;
they do not affect device operation, and all data sheet
timing and current specifications are met during an
update.
The device will power up with an output impedance
set at 50
W
. To guarantee optimum output driver
impedance after power-up, the SRAM needs 1,024
cycles to update the impedance. The user can operate
the part with fewer than 1,024 clock cycles, but optimal
output impedance is not guaranteed.
modest restart time of 1,024 clock cycles. Circuitry
automatically resets the DLL when the absence of the
input clock is detected. See Micron Technical Note TN-
54-02 for more information on clock DLL start-up pro-
cedures.
Optional-use echo clocks are provided to precisely
indicate data validity. Data changes occur very near to
the rising edges of CQ and CQ#.
Single Clock Mode
The SRAM can be used with the single K, K# clock
pair by tying C and C# HIGH. In this mode, the SRAM
will use K and K# in place of C and C#. This mode pro-
vides the most rapid data output but does not com-
pensate for system clock skew and flight times.
The output echo clocks are precise references to
output data. CQ and CQ# are both rising edge and fall-
ing edge accurate and are 180° out of phase. Either or
both may be used for output data capture. K or C rising
edge triggers CQ rising and CQ# falling edge. CQ rising
edge indicates first data response for QDRI and DDRI
(version 1, non-DLL) SRAM, while CQ# rising edge
indicates first data response for QDRII and DDRII (ver-
sion 2, DLL) SRAM.
Depth Expansion
Depth expansion is easily done by providing a new
LD# signal for each bank. R/W# can be shared among
all SRAMs in the system if driver fanout permits.
Clock Considerations
This device utilizes internal delay-locked loops for
maximum output, data valid window. It can be placed
into a stopped-clock state to minimize power, with a
36Mb: 1.8V V
DD
, HSTL, QDRB2 SRAM
MT57W2MH18C_B.fm – Rev. B, Pub. 2/03
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V V
DD
, HSTL, DDR SIO SRAM
Figure 2: Functional Block Diagram
4 Meg x 8; 4 Meg x 9; 2 Meg x 18; 1 Meg x 36
n
ADDRESS
LD#
R/W#
K
K#
n
ADDRESS
REGISTRY
& LOGIC
R/W#
NWx# or BW0#
a
DATA
REGISTRY
& LOGIC
2a
WR
RE
I G
T
E 2
WD
RR
I I
T V
EE
R
2 xa
MEMORY
ARRAY
n
D (Data In)
LD#
K
K#
K
S
EA
NM
SP
ES
2a
MUX
RO
EU
GT
P
U
A
T
C
2a
O
U
T
P
U
T
S
E
L
E
C
T
O
U
T
P
U
T
B
U
F
F
E
R
a
Q
(Data Out)
2
C,C#
or
K,K#
CQ
CQ#
NOTE:
1. Figure 2 illustrates simplified device operation. See truth table, ball descriptions, and timing diagrams for detailed
information.
2. For 4 Meg x 8, n = 22, a = 8; NWx# = 2 separate nibble writes.
For 4 Meg x 9, n = 22, a = 9; BWx# = 1 separate byte write.
For 2 Meg x 18, n = 21, a = 18; BWx# = 2 separate byte writes.
For 1 Meg x 36, n = 20, a = 36; BWx# = 4 separate byte writes.
36Mb: 1.8V V
DD
, HSTL, QDRB2 SRAM
MT57W2MH18C_B.fm – Rev. B, Pub. 2/03
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V V
DD
, HSTL, DDR SIO SRAM
Figure 3: Application Example
ZQ
Q
B B
CQ
WW
CQ#
0 1
R/W LD
# #
# # C C#
K
K#
SRAM 1
R = 250Ω
SRAM 2
B B
WW
R/W LD
0 1
# #
# #
R = 250Ω
ZQ
Q
CQ
CQ#
C C# K K#
Vt
R
D
SA
D
SA
BUS
MASTER
(CPU
SRAM 1 Input CQ
or
SRAM 1 Input CQ#
ASIC)
SRAM 4 Input CQ
SRAM 4 Input CQ#
Return CLK
Source CLK
Return CLK#
Source CLK#
Vt
Vt
R = 50Ω Vt = V
REF
DATA IN
DATA OUT
Address
R/W#
LD#
BW#
R
Vt
Vt
NOTE:
1. In this approach, the second clock pair drives the C and C# clocks but is delayed such that return data meets setup
and hold times at the bus master.
2. Consult Micron Technical Notes for more thorough discussions of clocking schemes.
3. Data capture is possible using only one of the two signals. CQ and CQ# clocks are optional use outputs.
4. For high frequency applications (200 MHz and faster) the CQ and CQ# clocks (for data capture) are recommended
over the C and C# clocks (for data alignment). The C and C# clocks are optional use inputs.
36Mb: 1.8V V
DD
, HSTL, QDRB2 SRAM
MT57W2MH18C_B.fm – Rev. B, Pub. 2/03
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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