Preliminary Data Sheet
November 2000
T9000
ISDN Network Termination Node (NTN) Device
1 Description
The T9000 is an ISDN network termination node
device that is highly integrated and provides a low-
cost solution to support the following:
s
s
General-purpose I/O (GPIO) ports with interrupt
capability for interfacing to SLICs, codecs, DTMF
decoders, and other peripheral devices.
Three low-power, general-purpose comparators.
Two 100 kHz programmable PWM outputs with an
automatic sine wave generation mode to support
ringing, pulse metering, etc.
20 kHz—200 kHz programmable dc/dc converter
synchronization output.
JTAG boundary scan on all digital pins.
Power-saving mode.
— In this mode, the unused interfaces of the
T9000, such as, microcontroller, PWMs, and
comparator can remain in powerdown mode,
thus resulting in significant reduction in power
consumption (see Section 20.2, Power Con-
sumption).
Packaged in a 100-pin TQFP (thin quad flat pkg).
5 V power supply.
Operating temperature range: –40 °C to +85 °C.
Integrated 80C32 microcontroller with the following
features:
— Programmable clock rates (MHz): 15.36, 7.68,
3.84, 1.92, 0.96.
— 4K internal SRAM.
— 64K internal ROM.
— Supports external ROM/RAM.
— Can be disabled via pin strap (sleep mode) for
use with an external emulator.
— Programmable watchdog timer.
s
s
All standard NT1 functions required to attach an
S/T interface device to an ISDN network. In addi-
tion, the T9000 also supports attachment of two
standard analog (POTS) telephones for communi-
cations over an ISDN network.
Intelligent network termination (INT/Smart NT1)
functions, with its built-in controller and support for
attachment of two analog phones for communica-
tions over an ISDN network.
A variation of the V5.1 signaling protocol called
narrowband multiservice delivery system (NMDS)
adopted by countries using the V5 signaling proto-
col (e.g., United Kingdom)
s
s
s
s
s
In addition, the T9000 can also be used for pair-gain
applications where support for more than one tele-
phone line is required without the installation of an
additional pair of wires from the telephone central
office to the customer premises.
s
s
s
s
2 Features
s
Complete interface to basic rate ISDN networks at
the S/T-interface and U-interface reference points.
U-interface (LT or NT operation) conforms to
ANSI*
T1.601 and ETSI TS 080 standards.
S/T-interface conforms to
ANSI
T1.605 standard,
ITU-T I.430 recommendation, and ETSI ETS 300
012 standard for the network termination (NT) side
of the network.
Low power consumption.
D-channel HDLC formatter with address recogni-
tion and integrated contention resolution scheme.
64-byte D-channel FIFOs.
GCI+ interface supporting GCI and generic TDM
modes for interfacing to a wide variety of POTS cir-
cuits.
s
s
External ROM and RAM (64K x 8 maximum each)
are accessed through an external data/address bus.
Support for ROM and RAM space above the 64K
limit can be accomplished by memory paging using
one or more GPIO signals as an external chip select.
Power management routines may be implemented
through the microcontroller to power down most of
the internal submodules, including the microcontrol-
ler itself. An autosleep mode is also included, allow-
ing the microcontroller to stop its internal clock and
be automatically restarted (microcontroller wake-up)
whenever any interrupt is triggered.
*
ANSI
is a registered trademark of American National Standards
Institute, Inc.
s
s
s
s
T9000
ISDN Network Termination Node (NTN) Device
Preliminary Data Sheet
November 2000
Table of Contents
Contents
Page
Contents
Page
1 Description................................................................1
2 Features ...................................................................1
3 Block Diagram ..........................................................6
4 Pin Information .........................................................7
5 Control Register Memory Space ............................15
6 Functional Modules ................................................17
6.1 80C32 Microcontroller Module (80C32 Block) ..17
6.2 Program Address Space...................................17
6.3 Data Address Space .........................................17
6.4 Timers ...............................................................17
6.5 Interrupts ...........................................................17
6.6 Interrupt Register Set ........................................18
6.7 Clock Generator................................................21
6.8 Watchdog Timer................................................22
6.9 On-Circuit Emulation (ONCE) Mode .................23
6.10 Emulation ........................................................23
6.11 Module I/O ......................................................23
6.12 Special Instructions for Using the Lucent
80C32 Block....................................................24
6.12.1 Port Configuration .....................................24
6.12.1.1 Ports 0 and 2 .......................................24
6.12.1.2 Port 1 ...................................................24
6.12.1.3 Port 3 ...................................................24
6.13 Serial Port Timing ...........................................25
6.14 External Program Memory Characteristics .....26
7 Transmission Superblock .......................................29
7.1 U-Interface Block (U Block)...............................29
7.2 S/T-Interface Block (S Block) ............................29
7.3 Data Flow/Activation Control Module (DFAC)...30
7.3.1 EOC State Machine (EOCSM) ....................30
7.3.2 Automatic EOC (AUTOEOC) Mode ............30
7.3.3 Manual EOC Mode......................................30
7.3.4 Data Flow Control........................................32
7.4 Microcontroller Access to Upstream and
Downstream B1 and B2 Channels....................32
7.5 LT Mode............................................................32
7.6 DFAC Register Set ...........................................33
8 Device Operation Control .......................................47
8.1 Device Operation Register ................................47
9 HDLC with FIFO Module ........................................52
9.1 HDLC Transmitter .............................................52
9.1.1 HDLC Transmitter Initialization....................52
9.2 HDLC Transmitter D-Channel Access ..............53
9.3 HDLC Receiver .................................................54
9.3.1 HDLC Receiver Initialization........................54
9.3.1.1 Overrun Condition..................................56
9.4 Address Recognition.........................................56
9.5 HDLC Register Set ...........................................58
10 GCI+ Interface Module ........................................ 69
10.1 TDM Mode (GCCF, GMODE[1:0] = 1x) ......... 69
10.2 GCI Modes (GCCF[GMODE(1:0)] = 0x) ........ 73
10.3 GCI-NT Mode (GCCF[GMODE(1:0)] = 00) .... 73
10.3.1 GCI-SCIT Mode (GCCF,
GMODE[1:0] = 01) ..................................... 75
10.3.2 Monitor Message Transfer ....................... 77
10.4 C/I Message Transfer..................................... 77
10.5 GCI+ Powerdown Mode................................. 77
10.6 GCI+ Loopbacks ............................................ 78
10.7 GCI+ Register Set.......................................... 79
11 GPIO Ports .......................................................... 85
11.1 GPIO Register Set ......................................... 86
12 PWM Module ....................................................... 93
12.1 PWM Manual/Timer Operation Mode............. 94
12.2 PWM Auto Operation (Sine) Mode................. 94
12.3 PWSM ROM................................................... 96
12.4 PWM Auto Mode Example ............................. 97
12.5 PWM Powerdown Mode............................... 100
12.6 PWM Module Register Set........................... 100
13 dc/dc Control Generator .................................... 104
13.1 dc/dc Control Generator Register Set .......... 104
14 Comparators...................................................... 105
14.1 Comparators Register Set............................ 106
14.2 Configuration Sequence .............................. 107
15 Test Mode.......................................................... 108
16 Loopbacks ......................................................... 109
17 Absolute Maximum Ratings............................... 110
18 Handling Precautions ........................................ 110
19 Recommended Operating Conditions ............... 110
20 Electrical Characteristics .................................... 111
20.1 Power Supply ................................................ 111
20.2 Power Consumption..................................... 111
20.3 S/T-Interface Receiver Common-Mode
Rejection ...................................................... 111
20.4 Pin Electrical Characteristics........................ 112
21 Crystal Characteristics....................................... 113
22 Timing Characteristics ....................................... 113
23 Application Diagrams......................................... 114
24 Outline Diagram................................................. 116
24.1 100-Pin TQFP .............................................. 116
25 Ordering Information.......................................... 117
26 Register Set Summary ...................................... 118
2
Lucent Technologies Inc.
Preliminary Data Sheet
November 2000
T9000
ISDN Network Termination Node (NTN) Device
Table of Contents
(continued)
Tables
Page
Tables
Page
Table 1. S/T-Interface Pins (6) ..................................8
Table 2. U-Interface Pins (7) .....................................8
Table 3. GCI+ Pins (5) ...............................................9
Table 4. GPIO Pins (24) ..........................................10
Table 5. 80C32 External Access Pins (27) ...............11
Table 6. Comparators (6) ........................................13
Table 7. JTAG Pins (4) ............................................13
Table 8. Miscellaneous Pins (2) ..............................14
Table 9. Oscillator Pins (2) ......................................14
Table 10. Power and Ground Pins ..........................14
Table 11. Control Register Memory Space ...............15
Table 12. GIR0: Global Interrupt Register 0
(0x00) ....................................................................18
Table 13. GIR1: Global Interrupt Register 1
(0x01) ....................................................................19
Table 14. GIE: Global Interrupt Enable Register
(0x02) .....................................................................20
Table 15. UPCK: Microcontroller Clock Control
Register (0x03) .....................................................21
Table 16. WDT: Microcontroller Watchdog Timer
Control (0x04) .......................................................22
Table 17. Port Direction Registers ...........................24
Table 18. Standard 80C32 RCLK/TCLK Options ....25
Table 19. Lucent 80C32 RCLK/TCLK Options ........25
Table 20. External Program Memory
Characteristics ........................................................26
Table 21. AUTOEOC = 1 Messages
(Data/Messages = 1) That Initiate Actions ............31
Table 22. DFCF: DFAC Configuration Register
(0x05) ....................................................................33
Table 23. DFR: Data Flow Register
(0x06) ....................................................................34
Table 24. UCR0: U-Interface Control Register #0
(0x07) ....................................................................35
Table 25. UCR1: U-Interface Control Register #1
(0x08) ....................................................................36
Table 26. USR0: U-Interface Status Register #0
(0x09) ....................................................................37
Table 27. USR1: U-Interface Status Register #1
(0x0A) ...................................................................37
Table 28. ECR0: EOC Control Register 0—Command
and Address (0x0B) ..............................................38
Table 29. ECR1: EOC Control Register 1—Message
(0x0C) ...................................................................39
Table 30. ESR0: EOC Status Register 0—Command
and Address (0x0D) ..............................................39
Table 31. ESR1: EOC Status Register 1—Message
(0x0E) ...................................................................39
Table 32. SCR0: S-Interface Control Register #0
(0x0F) ....................................................................40
Table 33. SCR1: S-Interface Control Register #1
(0x10) ....................................................................41
Table 34. SSR: S-Interface Status Register
(0x11) ................................................................... 42
Table 35. MFR0: Multiframe Register, Q-Chan-
nel Data (0x12) .................................................... 43
Table 36. MFR1: Multiframe Register, S-Sub-
channel Data (0x13) ............................................. 43
Table 37. UIR: U-Interface Interrupt Register
(0x14) ................................................................... 44
Table 38. UIE: U-Interface Interrupt Enable
(0x15) .................................................................... 45
Table 39. SIR: S-Interface Interrupt Register
(0x16) ................................................................... 46
Table 40. SIE: S-Interface Interrupt Enable Register
(0x17) .................................................................... 46
Table 41. DOCR: Device Operation Control
Register (0x50) ...................................................... 47
Table 42. B1UP: B1-Channel Upstream Data
from GCI to U-interface (0x51)............................... 47
Table 43. B2UP: B2-Channel Upstream Data
from GCI to U-interface (0x52)............................... 48
Table 44. B1DN: B1-Channel Downstream Data
from U-Interface to GCI (0x53) .............................. 48
Table 45. B2DN: B2-Channel Downstream Data
from U-Interface to GCI (0x54) .............................. 48
Table 46. Reserved 1: Reserved Register for
Internal Use (0x55) ................................................ 49
Table 47. Reserved 2: Reserved Register for
Internal Use (0x56) ................................................ 49
Table 48. Reserved 3: Reserved Register for
Internal Use (0x57) ................................................ 49
Table 49. Reserved 4: Reserved Register for
Internal Use (0x58) ................................................ 50
Table 50. Reserved 5: Reserved Register for
Internal Use (0x59) ................................................ 50
Table 51. Reserved 6: Reserved Register for
Internal Use (0x5A) ................................................ 50
Table 52. Reserved 7: Reserved Register for
Internal Use (0x5B) ................................................ 50
Table 53. Reserved 8: Reserved Register for
Internal Use (0x5C) ................................................ 51
Table 54. Reserved 9: Reserved Register for
Internal Use (0x5D) ................................................ 51
Table 55. HTCF: HDLC Transmitter Configuration
Register (0x18) .................................................... 58
Table 56. HRCF: HDLC Receiver Configuration
Register (0x19) .................................................... 59
Table 57. HTTH: HDLC Transmit FIFO Threshold
(0x1A) .................................................................. 60
Table 58. HRTH: HDLC Receive FIFO Threshold
(0x1B) .................................................................. 60
Table 59. HTSA: HDLC Transmit FIFO Space
Available (0x1C) ................................................... 61
Lucent Technologies Inc.
3
T9000
ISDN Network Termination Node (NTN) Device
Preliminary Data Sheet
November 2000
Table of Contents
(continued)
Tables
Page
Tables
Page
Table 60. HRDA: HDLC Receive FIFO Data
Available (0x1D) ....................................................61
Table 61. HTX: HDLC Transmit Data (0x1E) ..........61
Table 62. HTXL: HDLC Transmit Data Last Byte
(0x1F) ....................................................................62
Table 63. HRX: HDLC Receive Data (0x20) ...........62
Table 64. HSCR: HDLC SAPI C/R Bit Mask
(0x21) ....................................................................62
Table 65. HSM0: HDLC SAPI Match Pattern 0
(0x22) ....................................................................63
Table 66. HTM0: HDLC TEI Match Pattern 0
(0x23) ....................................................................63
Table 67. HSM1: HDLC SAPI Match Pattern 1
(0x24) ....................................................................63
Table 68. HTM1: HDLC TEI Match Pattern 1
(0x25) ....................................................................64
Table 69. HSM2: HDLC SAPI Match Pattern 2
(0x26) ....................................................................64
Table 70. HTM2: HDLC TEI Match Pattern 2
(0x27) ....................................................................64
Table 71. HSM3: HDLC SAPI Match Pattern 3
(0x28) ....................................................................64
Table 72. HTM3: HDLC TEI Match Pattern 3
(0x29) ....................................................................65
Table 73. HSMOD: HDLC SAPI Modifier Register
(0x2A) ....................................................................65
Table 74. HTMOD: HDLC TEI Modifier Register
(0x2B) ....................................................................66
Table 75. HIR: HDLC Interrupt Register (0x2C) ......67
Table 76. HIE: HDLC Interrupt Enable 15 (0x2D) ...68
Table 77. GCI+ Interface Signals ............................69
Table 78. TDM Data Rate and Clock Options ..........70
Table 79. GCI-TE Data-Slot Association ..................76
Table 80. GCCF: GCI+ Configuration Register
(0x2E) ...................................................................79
Table 81. GCOF1: GCI PFS1 Offset Select
(0x2F) ....................................................................80
Table 82. GCOF2: GCI PFS2 Offset Select
(0x30) ....................................................................80
Table 83. GCDMD: GCI Downstream (Transmit)
Monitor Data (0x31) ..............................................81
Table 84. GCDML: GCI Downstream (Transmit)
Monitor Data Last (0x32) ......................................81
Table 85. GCUMD: GCI Upstream (Receive) Monitor
Data (0x33) ...........................................................81
Table 86. GCDCI: GCI Downstream (Transmit) C/I
Data (0x34) ...........................................................82
Table 87. GCUCI: GCI Upstream (Receive) C/I
Data (0x35) ...........................................................82
Table 88. GCIR: GCI Interrupt Register (0x36) .......83
Table 89. GCIE: GCI Interrupt Enable (0x37) ..........84
Table 90. GPDIR0: GPIO Port 0 Pin Direction
(0x38) ....................................................................86
4
Table 91. GPDIR1: GPIO Port 1 Pin Direction
(0x39) ................................................................... 87
Table 92. GPDIR2: GPIO Port 2 Pin Direction
(0x3A) .................................................................. 87
Table 93. GPAF0: GPIO Alternate Function
Register #0 (0x3B) ............................................... 88
Table 94. GPAF1: GPIO Alternate Function
Register #1 (0x3C) ............................................... 89
Table 95. GPD0: GPIO Port 0 Data Register
(0x3D) .................................................................. 89
Table 96. GPD1: GPIO Port 1 Data Register
(0x3E) .................................................................. 90
Table 97. GPD2: GPIO Port 2 Data Register
(0x3F) ................................................................... 90
Table 98. GPLEI: GPIO Level-Edge-Triggered
Interrupt Control (0x40) ........................................ 90
Table 99. GPPOL: GPIO Interrupt Polarity
Control (0x41) ...................................................... 91
Table 100. GPIR: GPIO Interrupt Register
(0x42) ................................................................... 91
Table 101. GPIE: GPIO Interrupt Enable
(0x43) ................................................................... 92
Table 102. ROM Code ............................................. 96
Table 103. PWM Sine Modulator Programming
Example ............................................................... 98
Table 104. PW0CF: Pulse-Width Modulator 0
Configuration (0x44) .......................................... 100
Table 105. PW0VH: Pulse-Width Modulator 0
Pulse-Width Value, High Byte (0x45) ................. 101
Table 106. PW0VL: Pulse-Width Modulator 0
Pulse-Width Value, Low Byte (0x46) ................. 101
Table 107. PW1CF: Pulse-Width Modulator 1
Configuration (0x47) .......................................... 102
Table 108. PW1VH: Pulse-Width Modulator 1
Pulse-Width Value, High Byte (0x48) ................. 103
Table 109. PW1VL: Pulse-Width Modulator 1
Pulse-Width Value, Low Byte (0x49) ................. 103
Table 110. PWIR: Pulse-Width Modulator Interrupt
Register (0x4A) .................................................. 103
Table 111. DCCF: dc/dc Configuration Register
(0x4B) ................................................................ 104
Table 112. Comparator Characteristics ................ 106
Table 113. CME: Comparator Enable (0x4C) ....... 106
Table 114. CMT: Comparator Transition Polarity
(0x4D) ................................................................ 106
Table 115. CMIR: Comparator Interrupt Register
(0x4E) ................................................................ 107
Table 116. CMIE: Comparator Interrupt Enable
(0x4F) ................................................................. 107
Lucent Technologies Inc.
Preliminary Data Sheet
November 2000
T9000
ISDN Network Termination Node (NTN) Device
Table of Contents
(continued)
Tables
Page
Figures
Page
Table 117. Absolute Maximum Ratings ..................110
Table 118. ESD Threshold Voltage ........................110
Table 119. Recommended Operating Conditions .110
Table 120. Power Consumption ............................111
Table 121. S/T-Interface Receiver Common-Mode
Rejection ...............................................................111
Table 123. Digital dc Characteristics (Over
Operating Ranges)................................................112
Table 123. Fundamental Mode Crystal
Characteristics ......................................................113
Table 124. Internal PLL Characteristics ..................113
Table 126. MTC (Master Timing Clock)
Requirements and Characteristics (LT Mode) ......113
Table 126. Register Set Summary Global
Registers .............................................................118
Table 127. Register Set Summary DFAC
Registers .............................................................118
Table 128. Register Set Summary U-Interface
Control Registers ..................................................118
Table 129. Register Set Summary EOC
Control Registers ................................................119
Table 130. Register Set Summary S-Interface
Registers ..............................................................119
Table 131. Register Set Summary Multiframe
Registers .............................................................119
Table 132. Register Set Summary U-Interface
Interrupt Registers ..............................................119
Table 133. Register Set Summary S-Interface
Interrupt Registers ...............................................120
Table 134. Register Set Summary HDLC
Registers ..............................................................121
Table 135. Register Set Summary GCI+
Registers ..............................................................123
Table 136. Register Set Summary GPIO
Registers ..............................................................124
Table 137. Register Set Summary PWM
Registers ..............................................................125
Table 138. Register Set Summary dc/dc
Register ................................................................125
Table 139. Register Set Summary Comparator
Registers ..............................................................126
Figure 1. NTN Block Diagram..................................... 6
Figure 2. T9000 Pinout ............................................... 7
Figure 3. NTN Data Memory Address Space ........... 18
Figure 4. External Program Memory Read Cycle ..... 27
Figure 5. External Data Memory Read Cycle ........... 27
Figure 6. External Data Memory Write Cycle ........... 28
Figure 7. Downstream EOC Analysis (AUTOEOC = 1)
and Upstream EOC Processing ............................. 31
Figure 8. 2B+D Data Flow Block Diagram................ 32
Figure 9. HDLC Transmitter FIFO ............................ 53
Figure 10. HDLC Receiver Status Word................... 54
Figure 11. HDLC Receiver FIFO Snapshot
Sequence............................................................... 55
Figure 12. DLCI Extension and Function of
SAPI0M-TEI0M Bits ............................................... 57
Figure 13. GCI+ Interface, TDM Mode Timing,
Double Clock Mode: GCCF[CKMODE] = 0,
GCCF[GMODE(1:0)] = 1x ...................................... 71
Figure 14. GCI+ Interface, TDM Mode Timing,
Single Clock Mode: GCCF[CKMODE] = 1,
GCCF[GMODE(1)] = 1........................................... 72
Figure 15. NTN/T8503 Glueless TDM
Interconnection ...................................................... 72
Figure 16. GCI-NT Frame Structure ......................... 74
Figure 17. GCI-NT Timing Diagram.......................... 74
Figure 18. GCI-TE Mode Frame Structure ............... 76
Figure 19. GCI Loopback Logic ................................ 78
Figure 20. GPIO Pin Capabilities Summary ............. 86
Figure 21. Pulse-Width Modulated Output Signal .... 93
Figure 22. PWMCNTRL Architecture ....................... 95
Figure 23. Widths of PWM Pulses Generated with
a 2.5%—97.5% Modulation Width ......................... 99
Figure 24. (A) CMV When CME Is a Periodic
Pulse and (B) CMV When CMV Is Static ............. 105
Figure 25. Location of the Loopback
Configurations ...................................................... 109
Figure 26. NT1 Application ..................................... 114
Figure 27. NT1+ Application ................................... 114
Figure 28. Pair Gain Application ............................. 115
Lucent Technologies Inc.
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
