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Datasheet> 器件分类 > 存储> 存储> IDT71V547S11PF
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IDT71V547S11PF

产品描述ZBT SRAM, 128KX36, 11ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
产品类别存储    存储   
文件大小161KB，共19页
制造商IDT (Integrated Device Technology)
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IDT71V547S11PF概述

ZBT SRAM, 128KX36, 11ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100

IDT71V547S11PF规格参数

参数名称属性值
是否无铅含铅
是否Rohs认证不符合
厂商名称IDT (Integrated Device Technology)
零件包装代码QFP
包装说明14 X 20 MM, PLASTIC, TQFP-100
针数100
Reach Compliance Codenot_compliant
ECCN代码3A991.B.2.A
最长访问时间11 ns
最大时钟频率 (fCLK)71 MHz
I/O 类型COMMON
JESD-30 代码R-PQFP-G100
JESD-609代码e0
长度20 mm
内存密度4718592 bit
内存集成电路类型ZBT SRAM
内存宽度36
湿度敏感等级3
功能数量1
端口数量1
端子数量100
字数131072 words
字数代码128000
工作模式SYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织128KX36
输出特性3-STATE
可输出YES
封装主体材料PLASTIC/EPOXY
封装代码LQFP
封装等效代码QFP100,.63X.87
封装形状RECTANGULAR
封装形式FLATPACK, LOW PROFILE
并行/串行PARALLEL
峰值回流温度（摄氏度）240
电源3.3 V
认证状态Not Qualified
座面最大高度1.6 mm
最大待机电流0.01 A
最小待机电流3.14 V
最大压摆率0.2 mA
最大供电电压 (Vsup)3.465 V
最小供电电压 (Vsup)3.135 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层Tin/Lead (Sn85Pb15)
端子形式GULL WING
端子节距0.65 mm
端子位置QUAD
处于峰值回流温度下的最长时间20
宽度14 mm

IDT71V547S11PF文档预览

128K X 36, 3.3V Synchronous
IDT71V547
SRAM with ZBT™ Feature, Burst
Counter and Flow-Through Outputs
Features
128K x 36 memory configuration, flow-through outputs
Supports high performance system speed - 95 MHz
(8ns Clock-to-Data Access)
ZBT
TM
Feature - No dead cycles between write and read
cycles
Internally synchronized signal eliminates the need to
control
OE
Single R/W (READ/WRITE) control pin
W
4-word burst capability (Interleaved or linear)
Individual byte write (BW
1
-
BW
4
) control (May tie active)
BW
Three chip enables for simple depth expansion
Single 3.3V power supply (±5%)
Packaged in a JEDEC standard 100-pin TQFP package
The IDT71V547 contains address, data-in and control signal registers.
The outputs are flow-through (no output data register). Output enable is
the only asynchronous signal and can be used to disable the outputs at
any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V547 to
be suspended as long as necessary. All synchronous inputs are
ignored when
CEN
is high and the internal device registers will hold
their previous values.
There are three chip enable pins (CE
1
, CE
2
,
CE
2
) that allow the user
to deselect the device when desired. If any one of these three is not active
when ADV/LD is low, no new memory operation can be initiated and any
burst in progress is stopped. However, any pending data transfers (reads
or writes) will be completed. The data bus will tri-state one cycle after the
chip was deselected or write initiated.
The IDT71V547 has an on-chip burst counter. In the burst mode, the
IDT71V547 can provide four cycles of data for a single address presented
to the SRAM. The order of the burst sequence is defined by the
LBO
input
pin. The
LBO
pin selects between linear and interleaved burst sequence.
The ADV/LD signal is used to load a new external address (ADV/LD =
LOW) or increment the internal burst counter (ADV/LD = HIGH).
The IDT71V547 SRAM utilizes IDT's high-performance, high-volume
3.3V CMOS process, and is packaged in a JEDEC Standard 14mm x
20mm 100-pin thin plastic quad flatpack (TQFP) for high board density.
x
x
x
x
x
x
x
x
x
x
Description
The IDT71V547 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM organized as 128K x 36 bits. It is designed to eliminate
dead bus cycles when turning the bus around between reads and writes,
or writes and reads. Thus it has been given the name ZBT
TM
, or Zero Bus
Turn-around.
Address and control signals are applied to the SRAM during one clock
cycle, and on the next clock cycle, its associated data cycle occurs, be it
read or write.
Pin Description Summary
A
0
- A
16
CE
1
, CE
2
,
CE
2
OE
R/W
CEN
BW
1
,
BW
2
,
BW
3
,
BW
4
CLK
ADV/LD
LBO
I/O
0
- I/O
31
, I/O
P1
-
I/O
P4
V
DD
V
SS
Address Inputs
Three Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance Burst Address / Load New Address
Linear / Interleaved Burst Order
Data Input/Output
3.3V Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Static
Static
3822 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
DECEMBER 1999
DSC-3822/03
1
©1999 Integrated Device Technology, Inc.
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
™
Commercial and Industrial Temperature Ranges
Pin Definitions
(1)
Symbol
A
0
- A
16
Pin Function
Address Inputs
I/O
I
Active
N/A
Description
Synchronous Address inputs. The address register is triggered by a combination
of the rising edge of CLK, ADV/LD Low,
CEN
Low and true chip enables.
ADV/LD is a synchronous input that is used to load the internal registers with new
address and control when it is sampled low at the rising edge of clock with the
chip selected. When ADV/LD is low with the chip deselected, any burst in
progress is terminated. When ADV/LD is sampled high then the internal burst
counter is advanced for any burst that was in progress. The external addresses
are ignored when ADV/LD is sampled high.
R/W signal is a synchronous input that identifies whether the current load cycle
initiated is a Read or Write access to the memory array. The data bus activity for
the current cycle takes place one clock cycle later.
Synchronous Clock Enable Input. When
CEN
is sampled high, all other
synchronous inputs, including clock are ignored and outputs remain unchanged.
The effect of
CEN
sampled high on the device outputs is as if the low to high
clock transition did not occur. For normal operation,
CEN
must be sampled low at
rising edge of clock.
Synchronous byte write enables. Enable 9-bit byte has its own active low byte
write enable. On load write cycles (When R/W and ADV/LD are sampled low) the
appropriate byte write signal (BW
1
-
BW
4
) must be valid. The byte write signal
must also be valid on each cycle of a burst write. Byte Write signals are ignored
when R/W is sampled high. The appropriate byte(s) of data are written into the
device one cycle later.
BW
1
-
BW
4
can all be tied low if always doing write to the
entire 36-bit word.
Synchronous active low chip enable.
CE
1
and
CE
2
are used with CE
2
to
enable the IDT71V547. (CE
1
or
CE
2
sampled high or CE
2
sampled low) and
ADV/LD low at the rising edge of clock, initiates a deselect cycle. This device has
a one cycle deselect, i.e., the data bus will tri-state one clock cycle after deselect
is initiated.
Synchronout active high chip enable. CE
2
is used with
CE
1
and
CE
2
to enable
the chip. CE
2
has inverted polarity but otherwise identical to
CE
1
and
CE
2
.
This is the clock input to the IDT71V547. Except for
OE,
all timing references for
the device are made with respect to the rising edge of CLK.
Data input/output (I/O) pins. The data input path is registered, triggered by the
rising edge of CLK. The data output path is flow-through (no output register).
Burst order selection input. When
LBO
is high the Interleaved burst sequence is
selected. When
LBO
is low the Linear burst sequence is selected.
LBO
is a static
DC input.
Asynchronous output enable.
OE
must be low to read data from the 71V547.
When
OE
is high the I/O pins are in a high-impedance state.
OE
does not need
to be actively controlled for read and write cycles. In normal operation,
OE
can be
tied low.
3.3V power supply input.
Ground pin.
3822 tbl 02
ADV/LD
Address/Load
I
N/A
R/W
Read/Write
I
N/A
CEN
Clock Enable
I
LOW
BW
1
-
BW
4
Individual Byte
Write Enables
I
LOW
CE
1
,
CE
2
Chip Enables
I
LOW
CE2
CLK
I/O
0
- I/O
31
I/O
P1 -
I/O
P4
LBO
Chip Enable
Clock
Data Input/Output
Linear Burst
Order
Output Enable
I
I
I/O
I
HIGH
N/A
N/A
LOW
OE
I
LOW
V
DD
V
SS
Power Supply
Ground
N/A
N/A
N/A
N/A
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
2
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
™
Commercial and Industrial Temperature Ranges
Functional Block Diagram
LBO
Address A [0:16]
C E
1
, CE2
C E
2
R/W
C EN
ADV/LD
BW
x
D
Clk
D
Q
Control
D
Q
128K x 36 BIT
MEMORY ARRAY
Address
Input Register
DI
DO
Q
Control Logic
Mux
Clock
Sel
OE
Gate
,
Data I/O [0:31], I/O P[1:4]
3822 drw 01
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
V
SS
0V
0V
V
DD
3.3V±5%
3.3V±5%
3822 tbl 03
Recommended DC Operating
Conditions
Symbol
V
DD
V
SS
V
IH
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
Min.
3.135
0
2.0
2.0
-0.5
(1)
Typ.
3.3
0
____
____
____
Max.
3.465
0
4.6
V
DD
+0.3
(2)
0.8
Unit
V
V
V
V
V
3822 tbl 04
NOTES:
1. V
IL
(min.) = –1.0V for pulse width less than t
CYC
/2, once per cycle.
2. V
IH
(max.) = +6.0V for pulse width less than t
CYC
/2, once per cycle.
3
6.42
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
™
Commercial and Industrial Temperature Ranges
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/O
P3
I/O
16
I/O
17
V
DD
V
SS
I/O
18
I/O
19
I/O
20
I/O
21
V
SS
V
DD
I/O
22
I/O
23
V
SS
(1)
V
DD
V
DD
V
SS
I/O
24
I/O
25
V
DD
V
SS
I/O
26
I/O
27
I/O
28
I/O
29
V
SS
V
DD
I/O
30
I/O
31
I/O
P4
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
C EN
OE
ADV/LD
NC
(2)
NC
(2)
A
8
A
9
Pin Configuration
A
6
A
7
CE
1
CE
2
BW
4
BW
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
PK100-1
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
P2
I/O
15
I/O
14
V
DD
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DD
I/O
9
I/O
8
V
SS
V
SS
V
DD
V
SS
I/O
7
I/O
6
V
DD
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DD
I/O
1
I/O
0
I/O
P1
LBO
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
A
15
A
16
Top View
TQFP
3822 drw 02
NOTES:
1. Pin 14 does not have to be connected directly to V
SS
as long as the input voltage is < V
IL
.
2. Pins 83 and 84 are reserved for future A
17
(8M) and A
18
(16M) respectively.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect to GND
Terminal Voltage
with Respect to GND
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
-0.5 to +4.6
-0.5 to V
DD
+0.5
0 to +70
-55 to +125
-55 to +125
2.0
50
Unit
V
V
o
(T
A
= +25°C, f = 1.0MHz, TQFP package)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
5
7
Unit
pF
pF
3822 tbl 06
Capacitance
V
TERM
(3)
T
A
T
BIAS
T
STG
P
T
I
OUT
C
C
C
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
o
o
W
mA
3822 tbl 05
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. V
DD
and Input terminals only.
3. I/O terminals.
4
IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT™ Feature, Burst Counter and Flow-Through Outputs
™
Commercial and Industrial Temperature Ranges
Synchronous Truth Table
(1)
CEN
L
L
L
L
L
L
H
R/W
L
H
X
X
X
X
X
Chip
(5)
Enable
Select
Select
X
X
Deselect
X
X
ADV/LD
L
L
H
H
L
H
X
BW
x
Valid
X
Valid
X
X
X
X
ADDRESS
USED
External
External
Internal
Internal
X
X
X
PREVIOUIS CYCLE
X
X
LOAD WRITE/
BURST WRITE
LOAD READ/
BURST READ
X
DESELECT / NOOP
X
CURRENT CYCLE
LOAD WRITE
LOAD READ
BURST WRITE
(Advance Burst Counter)
(2)
BURST READ
(Advance Burst Counter)
(2)
DESELECT or STOP
(3)
NOOP
SUSPEND
(4)
I/O
(1 cycle later)
D
(7)
Q
(7)
D
(7)
Q
(7)
HiZ
HiZ
Previous Value
3822 tbl 07
NOTES:
1. L = V
IL
, H = V
IH
, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature
of the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE
1
, or
CE
2
is sampled high or CE
2
is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus
will tri-state one cycle after deselect is initiated.
4. When
CEN
is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the
I/Os remains unchanged.
5. To select the chip requires
CE
1
= L,
CE
2
= L and CE
2
= H on these chip enable pins. The chip is deselected if either one of thechip enable is false.
6. Device Outputs are ensured to be in High-Z during device power-up.
7. Q - data read from the device, D - data written to the device.
Partial Truth Table for Writes
(1)
Operation
READ
WRITE ALL BYTES
WRITE BYTE 1 (I/O [0:7], I/O
P1
)
(2)
WRITE BYTE 2 (I/O [8:15], I/O
P2
)
(2)
WRITE BYTE 3 (I/O [16:23], I/O
P3
)
(2)
WRITE BYTE 4 (I/O [24:31], I/O
P4
)
(2)
NO WRITE
NOTES:
1. L = V
IL
, H = V
IH
, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
R/W
H
L
L
L
L
L
L
BW
1
X
L
L
H
H
H
H
BW
2
X
L
H
L
H
H
H
BW
3
X
L
H
H
L
H
H
BW
4
X
L
H
H
H
L
H
3822 tbl 08
5
6.42
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器件捷径:   E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

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