74ACQ245 • 74ACTQ245 Quiet Series¥ Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs
July 1989
Revised March 2005
74ACQ245 • 74ACTQ245
Quiet Series¥ Octal Bidirectional Transceiver
with 3-STATE Inputs/Outputs
General Description
The ACQ/ACTQ245 contains eight non-inverting bidirec-
tional buffers with 3-STATE outputs and is intended for bus-
oriented applications. Current sinking capability is 24 mA at
both the A and B ports. The Transmit/Receive (T/R) input
determines the direction of data flow through the bidirec-
tional transceiver. Transmit (active-HIGH) enables data
from A Ports to B Ports; Receive (active-LOW) enables
data from B Ports to A Ports. The Output Enable input,
when HIGH, disables both A and B ports by placing them in
a HIGH Z condition.
The ACQ/ACTQ utilizes Fairchild Quiet Series
¥
technol-
ogy to guarantee quiet output switching and improve
dynamic threshold performance. FACT Quiet Series
¥
fea-
tures GTO
¥
output control and undershoot corrector in
addition to a split ground bus for superior performance.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Improved latch-up immunity
s
3-STATE outputs drive bus lines or buffer memory
address registers
s
Outputs source/sink 24 mA
s
Faster prop delays than the standard ACT245
Ordering Code:
Order Number
74ACQ245SC
74ACQ245SJ
74ACQ245PC
74ACTQ245SC
74ACTQ245SJ
74ACTQ245QSC
74ACTQ245MSA
74ACTQ245MTC
74ACTQ245MTCX_NL
(Note 1)
74ACTQ245PC
Package
Number
M20B
M20D
N20A
M20B
M20D
MQA20
MSA20
MTC20
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
FACT
¥
, Quiet Series
¥
, FACT Quiet Series
¥
, and GTO
¥
are trademarks of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS010236
www.fairchildsemi.com
74ACQ245 • 74ACTQ245
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
V
I
0.5V to
7.0V
20 mA
20 mA
0.5V to V
CC
0.5V
20 mA
20 mA
0.5V to V
CC
0.5V
r
50 mA
r
50 mA
65
q
C to
150
q
C
r
300 mA
140
q
C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
ACQ
ACTQ
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate
'
V/
'
t
ACQ Devices
V
IN
from 30% to 70% of V
CC
V
CC
@ 3.0V, 4.5V, 5.5V
Minimum Input Edge Rate
'
V/
'
t
ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
Note 2:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
¥
circuits outside databook specifications.
0.5V
V
CC
0.5V
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
V
O
0.5V
V
CC
0.5V
40
q
C to
85
q
C
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
DC Latch-Up Source or
Sink Current
Junction Temperature (T
J
)
PDIP
125 mV/ ns
DC Electrical Characteristics for ACQ
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
IN
(Note 5)
I
OLD
I
OHD
I
CC
(Note 5)
I
OZT
Maximum Input
Leakage Current
Minimum Dynamic
Output Current (Note 4)
Maximum Quiescent
Supply Current
Maximum I/O
Leakage Current
5.5
5.5
5.5
5.5
4.0
75
mA
mA
V
OLD
V
OHD
V
IN
or GND
V
I
(OE)
V
IL
, V
IH
1.65V Max
3.85V Min
V
CC
5.5
0.002
0.001
0.001
T
A
Typ
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
25
q
C
T
A
40
q
C to
85
q
C
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
Guaranteed Limits
Units
V
OUT
V
Conditions
0.1V
or V
CC
0.1V
V
OUT
0.1V
V
or V
CC
0.1V
V
I
OUT
V
IN
50
P
A
V
IL
or V
IH
2.46
3.76
4.76
0.1
0.1
0.1
V
V
I
OH
I
OH
I
OH
I
OUT
V
IN
12 mA
24 mA
24 mA (Note 3)
50
P
A
V
IL
or V
IH
12 mA
24 mA
24 mA (Note 3)
V
CC
, GND
0.44
0.44
0.44
V
I
OL
I
OL
I
OL
V
I
r
0.1
r
1.0
P
A
75
40.0
P
A
r
0.3
r
3.0
P
A
V
I
V
O
V
CC
, GND
V
CC
, GND
3
www.fairchildsemi.com
74ACQ245 • 74ACTQ245
DC Electrical Characteristics for ACQ
Symbol
V
OLP
V
OLV
V
IHD
V
ILD
Parameter
Quiet Output
Maximum Dynamic V
OL
Quiet Output
Minimum Dynamic V
OL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
V
CC
(V)
5.0
5.0
5.0
5.0
T
A
Typ
1.1
(Continued)
T
A
25
q
C
40
q
C to
85
q
C
Units
Conditions
Figure 1, Figure 2
(Note 6)(Note 7)
Figure 1, Figure 2
(Note 6)(Note 7)
(Note 6)(Note 8)
(Note 6)(Note 8)
Guaranteed Limits
1.5
V
V
V
V
0.6
3.1
1.9
1.2
3.5
1.5
Note 3:
All outputs loaded; thresholds on input associated with output under test.
Note 4:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 5:
I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
Note 6:
DIP package.
Note 7:
Max number of outputs defined as (n). Data Inputs are driven 0V to 5V; one output @ GND.
Note 8:
Max number of Data Inputs (n) switching. (n
1) Inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (V
ILD
),
0V to threshold (V
IHD
), f 1 MHz.
DC Electrical Characteristics for ACTQ
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
4.5
5.5
4.5
5.5
I
IN
I
OZT
I
CCT
I
OLD
I
OHD
I
CC
V
OLP
V
OLV
V
IHD
V
ILD
Maximum Input Leakage Current
Maximum 3-STATE
Leakage Current
Maximum I
CC
/Input
Minimum Dynamic
Output Current (Note 10)
Maximum Quiescent Supply Current
Quiet Output
Maximum Dynamic V
OL
Quiet Output
Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
5.5
5.5
5.5
5.5
5.0
5.0
5.0
5.0
1.1
4.0
1.5
0.6
1.5
75
mA
mA
mA
5.5
5.5
0.001
0.001
T
A
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
25
q
C
T
A
40
q
C to
85
q
C
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
Guaranteed Limits
Units
V
V
V
V
OUT
V
OUT
I
OUT
V
IN
V
V
I
OH
I
OH
I
OUT
V
IN
V
I
OL
I
OL
V
I
V
I
V
O
V
I
V
OLD
Conditions
0.1V
0.1V
or V
CC
0.1V
or V
CC
0.1V
50
P
A
V
IL
or V
IH
24 mA
24 mA (Note 9)
50
P
A
V
IL
or V
IH
24 mA
24 mA (Note 9)
V
CC
, GND
V
IL
, V
IH
V
CC
, GND
V
CC
2.1V
1.65V Max
3.85V Min
V
CC
or GND
r
0.1
r
0.3
r
1.0
r
3.0
P
A
P
A
75
40.0
V
OHD
V
IN
P
A
V
V
V
V
Figure 1, Figure 2
(Note 11)(Note 12)
Figure 1, Figure 2
(Note 11)(Note 12)
(Note 11)(Note 13)
(Note 11)(Note 13)
0.6
1.9
1.2
1.2
2.2
0.8
Note 9:
All outputs loaded; thresholds on input associated with output under test.
Note 10:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 11:
DIP package.
Note 12:
Max number of outputs defined as (n). n
1 Data Inputs are driven 0V to 3V; one output @ GND.
Note 13:
Max number of Data Inputs (n) switching. (n
1) Inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (V
ILD
),
0V to threshold (V
IHD
) f 1 MHz.
www.fairchildsemi.com
4
74ACQ245 • 74ACTQ245
AC Electrical Characteristics for ACQ
V
CC
Symbol
t
PHL
t
PLH
t
PZL
t
PZH
t
PHZ
t
PLZ
t
OSHL
t
OSLH
Output to Output Skew (Note 15)
Data to Output
Voltage Range 3.3 is 3.3V
r
0.3V
Note 15:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
T
A
C
L
Min
2.0
1.5
3.0
2.0
1.0
1.0
25
q
C
50 pF
Typ
7.5
5.0
8.5
6.0
8.5
7.5
1.0
0.5
Max
10.0
6.5
13.0
8.5
14.5
9.5
1.5
1.0
T
A
40
q
C to
85
q
C
C
L
50 pF
Max
10.5
7.0
13.5
9.0
15.0
10.0
1.5
1.0
ns
ns
ns
ns
Units
Parameter
Propagation Delay
Data to Output
Output Enable Time
Output Disable Time
(V)
(Note 14)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Min
2.0
1.5
3.0
2.0
1.0
1.0
Note 14:
Voltage Range 5.0 is 5.0V
r
0.5V
AC Electrical Characteristics for ACTQ
V
CC
Symbol
t
PHL
t
PLH
t
PZL
, t
PZH
t
PHZ
, t
PLZ
t
OSHL
t
OSLH
Parameter
Propagation Delay
Data to Output
Output Enable Time
Output Disable Time
Output to Output Skew (Note 17)
Data to Output
5.0
5.0
5.0
2.0
1.0
7.0
8.0
0.5
9.0
10.0
1.0
2.0
1.0
9.5
10.5
1.0
ns
ns
ns
(V)
(Note 16)
5.0
Min
1.5
T
A
C
L
25
q
C
50 pF
Typ
5.5
Max
7.0
T
A
40
q
C to
85
q
C
C
L
50 pF
Max
7.5
ns
Units
Min
1.5
Note 16:
Voltage Range 5.0 is 5.0V
r
0.5V
Note 17:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
Capacitance
Symbol
C
IN
C
I/O
C
PD
Parameter
Input Capacitance
Input/Output Capacitance
Power Dissipation Capacitance
Typ
4.5
15
80.0
Units
pF
pF
pF
V
CC
V
CC
V
CC
OPEN
5.0V
5.0V
Conditions
5
www.fairchildsemi.com
无线连接
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
