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CY7C1421AV18-167BZXC: 产品描述DDR SRAM, 1MX36, 0.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165; 产品类别存储存储; 文件大小372KB，共24页; 制造商Cypress(赛普拉斯); 标准

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CY7C1421AV18-167BZXC概述

DDR SRAM, 1MX36, 0.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165

CY7C1421AV18-167BZXC规格参数

参数名称	属性值
是否无铅	不含铅
是否Rohs认证	符合
厂商名称	Cypress(赛普拉斯)
零件包装代码	BGA
包装说明	LBGA, BGA165,11X15,40
针数	165
Reach Compliance Code	compliant
ECCN代码	3A991.B.2.A
最长访问时间	0.5 ns
其他特性	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)	167 MHz
I/O 类型	COMMON
JESD-30 代码	R-PBGA-B165
JESD-609代码	e1
长度	17 mm
内存密度	37748736 bit
内存集成电路类型	DDR SRAM
内存宽度	36
湿度敏感等级	3
功能数量	1
端子数量	165
字数	1048576 words
字数代码	1000000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	1MX36
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	LBGA
封装等效代码	BGA165,11X15,40
封装形状	RECTANGULAR
封装形式	GRID ARRAY, LOW PROFILE
并行/串行	PARALLEL
峰值回流温度（摄氏度）	260
电源	1.5/1.8,1.8 V
认证状态	Not Qualified
座面最大高度	1.4 mm
最大待机电流	0.22 A
最小待机电流	1.7 V
最大压摆率	0.5 mA
最大供电电压 (Vsup)	1.9 V
最小供电电压 (Vsup)	1.7 V
标称供电电压 (Vsup)	1.8 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	20
宽度	15 mm

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PRELIMINARY

CY7C1417AV18

CY7C1428AV18

CY7C1419AV18

CY7C1421AV18

36-Mbit DDR-II SRAM 4-Word

Burst Architecture

Features

• 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)

• 250-MHz clock for high bandwidth

• 4-Word burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces

(data transferred at 500 MHz) @ 250 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) account for clock skew

and flight time mismatching

• Echo clocks (CQ and CQ) simplify data capture in

high-speed systems

• Synchronous internally self-timed writes

• 1.8V core power supply with HSTL inputs and outputs

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–V

)

• 15 x 17 x 1.4mm 1.0-mm pitch fBGA package,

165-ball (11 x 15 matrix)

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

Functional Description

The CY7C1417AV18, CY7C1428AV18, CY7C1419AV18, and

CY7C1421AV18 are 1.8V Synchronous Pipelined SRAM

equipped with DDR-II (Double Data Rate) architecture. The

DDR-II consists of an SRAM core with advanced synchronous

peripheral circuitry and a two-bit burst counter. Addresses for

Read and Write are latched on alternate rising edges of the

input (K) clock. Write data is registered on the rising edges of

both K and K. Read data is driven on the rising edges of C and

C if provided, or on the rising edge of K and K if C/C are not

provided. Each address location is associated with four 8-bit

words in the case of CY7C1417AV18 and four 9-bit words in

the case of CY7C1428AV18 that burst sequentially into or out

of the device. The burst counter always starts with “00” inter-

nally in the case of CY7C1417AV18 and CY7C1421AV18. On

CY7C1428AV18 and CY7C1419AV18, the burst counter takes

in the last two significant bits of the external address and

bursts four 18-bit words in the case of CY7C1428AV18, and

four 36-bit words in the case of CY7C1419AV18, sequentially

into or out of the device.

Asynchronous inputs include impedance match (ZQ).

Synchronous data outputs (Q, sharing the same physical pins

as the data inputs, D) are tightly matched to the two output

echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR-II SRAM in the

system design. Output data clocks (C/C) enable maximum

system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

Configurations

CY7C1417AV18 – 4M x 8

CY7C1428AV18 – 4M x 9

CY7C1419AV18 – 2M x 18

CY7C1421AV18 – 1M x 36

Selection Guide

250 MHz

Maximum Operating Frequency

Maximum Operating Current

250

TBD

200 MHz

200

TBD

167 MHz

167

TBD

Unit

MHz

Cypress Semiconductor Corporation

Document Number: 38-05618 Rev. *A

•

3901 North First Street

•

San Jose

CA 95134

•

408-943-2600

Revised August 11, 2004

CY7C1421AV18-167BZXC相似产品对比

	CY7C1421AV18-167BZXC	CY7C1419AV18-167BZXC	CY7C1417AV18-167BZXC	CY7C1428AV18-167BZXC
描述	DDR SRAM, 1MX36, 0.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165	DDR SRAM, 2MX18, 0.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165	DDR SRAM, 4MX8, 0.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165	DDR SRAM, 4MX9, 0.5ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
是否无铅	不含铅	不含铅	不含铅	不含铅
是否Rohs认证	符合	符合	符合	符合
零件包装代码	BGA	BGA	BGA	BGA
包装说明	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40
针数	165	165	165	165
Reach Compliance Code	compliant	compliant	compliant	compliant
ECCN代码	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
最长访问时间	0.5 ns	0.5 ns	0.5 ns	0.5 ns
其他特性	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)	167 MHz	167 MHz	167 MHz	167 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165
JESD-609代码	e1	e1	e1	e1
长度	17 mm	17 mm	17 mm	17 mm
内存密度	37748736 bit	37748736 bit	33554432 bit	37748736 bit
内存集成电路类型	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM
内存宽度	36	18	8	9
湿度敏感等级	3	3	3	3
功能数量	1	1	1	1
端子数量	165	165	165	165
字数	1048576 words	2097152 words	4194304 words	4194304 words
字数代码	1000000	2000000	4000000	4000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	70 °C	70 °C
组织	1MX36	2MX18	4MX8	4MX9
输出特性	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	LBGA	LBGA	LBGA	LBGA
封装等效代码	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL
峰值回流温度（摄氏度）	260	260	260	260
电源	1.5/1.8,1.8 V	1.5/1.8,1.8 V	1.5/1.8,1.8 V	1.5/1.8,1.8 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.4 mm	1.4 mm	1.4 mm	1.4 mm
最大待机电流	0.22 A	0.22 A	0.22 A	0.22 A
最小待机电流	1.7 V	1.7 V	1.7 V	1.7 V
最大压摆率	0.5 mA	0.5 mA	0.5 mA	0.5 mA
最大供电电压 (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V
最小供电电压 (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V
标称供电电压 (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V
表面贴装	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式	BALL	BALL	BALL	BALL
端子节距	1 mm	1 mm	1 mm	1 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM
处于峰值回流温度下的最长时间	20	20	20	20
宽度	15 mm	15 mm	15 mm	15 mm
厂商名称	Cypress(赛普拉斯)	Cypress(赛普拉斯)	-	Cypress(赛普拉斯)

CY7C1421AV18-167BZXC

CY7C1421AV18-167BZXC概述

CY7C1421AV18-167BZXC规格参数

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