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CY74FCT163374CPAC

产品描述Bus Driver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.240 INCH, 0.0196 INCH PITCH, TSSOP-48
产品类别逻辑    逻辑   
文件大小104KB,共6页
制造商Cypress(赛普拉斯)
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CY74FCT163374CPAC概述

Bus Driver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.240 INCH, 0.0196 INCH PITCH, TSSOP-48

CY74FCT163374CPAC规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称Cypress(赛普拉斯)
零件包装代码TSSOP
包装说明TSSOP, TSSOP48,.3,20
针数48
Reach Compliance Codenot_compliant
系列FCT
JESD-30 代码R-PDSO-G48
JESD-609代码e0
长度12.5 mm
负载电容(CL)50 pF
逻辑集成电路类型BUS DRIVER
最大I(ol)0.024 A
位数8
功能数量2
端口数量2
端子数量48
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装等效代码TSSOP48,.3,20
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源3/3.3 V
Prop。Delay @ Nom-Sup5.2 ns
传播延迟(tpd)5.2 ns
认证状态Not Qualified
座面最大高度1.1 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)2.7 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Tin/Lead (Sn/Pb)
端子形式GULL WING
端子节距0.5 mm
端子位置DUAL
触发器类型POSITIVE EDGE
宽度6.1 mm

文档预览

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3H374
fax id: 7051
CY74FCT163374
CY74FCT163H374
CY74FCT163LD374
CY74FCT163LDH374
16-Bit Registers
Features
• Low power, pin-compatible replacement for LCX, LPT,
LVC, LVCH & LVT families
• 5V tolerant inputs and outputs*
• 6 mA & 24 mA balanced drive outputs
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for reduced noise
• FCT-C speed at 5.2 ns
• Latch-up performance exceeds JEDEC standard no. 17
• Typical output skew < 250 ps
• Industrial temperature range of –40°C to +85°C
• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
• Typical
V
olp
(ground bounce) performance exceeds Mil
Std 883D
• V
CC
= 2.7V to 3.6V
• ESD (HBM) > 2000V
CY74FCT163H374
• Bus hold on data inputs
• Eliminates the need for external pull-up or pull-down
resistors
• *Devices with bus hold are not recommended for trans-
lating rail-to-rail CMOS signals to 3.3V logic levels
CY74FCT163LD2374
• Lite Drive™ option for low noise applications
• 6 mA balanced drive outputs
• FCT-A speed at 6.5 ns
• V
CC
= 3.0V to 3.6V
• ESD (HBM) > 1100V
Functional Description
These devices are 16-bit D-type registers designed for use as
buffered registers in high-speed, low power bus applications.
These devices can be used as two independent 8-bit registers
or as a single 16-bit register by connecting the output Enable
(OE) and Clock (CLK) inputs. The outputs are 24-mA balanced
output drivers with current limiting resistors to reduce the need
for external terminating resistors, and provide for minimal un-
dershoot and reduced ground bounce. Flow-through pinout
and small shrink packaging aid in simplifying board layout.
The CY74FCT163H374 and CY74FCT163LDH374 have “bus
hold” on the data inputs, which retain the input’s last state
whenever the source driving the input goes to high impedance.
This eliminates the need for pull-up/down resistors and pre-
vents floating inputs.
The CY74FCT163374 and the CY74FCT16LD374 are
designed with inputs and outputs capable of being driven by
5.0V buses, allowing them to be used in mixed voltage
systems as translators. The outputs are also designed with a
power off disable feature enabling them to be used in
applications requiring live insertion.
Logic Block Diagrams CY74FCT163374, CY74FCT163H374,
CY74FCT163LD374, CY74FCT163LDH374
Pin Configuration
SSOP/TSSOP
Top View
1
OE
1
O
1
1
O
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
CLK
1
D
1
1
D
2
1
OE
2
OE
GND
1
O
3
1
O
4
V
CC
1
O
5
2
O
1
1
O
6
GND
1
D
3
1
D
4
1
CLK
1
D
1
2
CLK
D
1
O
1
2
D
1
D
C
V
CC
1
D
5
1
D
6
C
GND
1
O
7
1
O
8
2
O
1
GND
1
D
7
1
D
8
2
D
1
2
D
2
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
2
O
2
GND
2
O
3
2
O
4
V
CC
2
O
5
2
O
6
GND
2
D
3
2
D
4
V
CC
2
D
5
2
D
6
GND
2
O
7
2
O
8
2
OE
GND
2
D
7
2
D
8
2
CLK
Lite Drive is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
3901 North First Street
San Jose
• CA 95134 •
408-943-2600
March 19, 1997 – Revised April 20, 1998
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