TSH151
WIDE BANDWIDTH AND MOS INPUTS
SINGLE OPERATIONAL AMPLIFIER
s
s
s
s
s
s
LOW DISTORTION
GAIN BANDWIDTH PRODUCT : 150MHz
UNITY GAIN STABLE
SLEW RATE : 200V/µs
VERY FAST SETTLING TIME : 70ns (0.1%)
VERY HIGH INPUT IMPEDANCE
DESCRIPTION
The TSH151 is a wideband monolithic operational
amplifier, internally compensated for unity-gain
stability.
The TSH151 features extremely high input imped-
ance (typically greater than 10
12
Ω)
allowing direct
interfacing with high impedance sources.
Low distortion, wide bandwidth and high linearity
make this amplifier suitable for RF and video ap-
plications. Short circuit protection is provided by
an internal current-limiting circuit.
The TSH151 has internal electrostatic discharge
(ESD)
protection
circuits
and
fulfills
MILSTD883C-Class2.
ORDER CODE
Package
Part Number
TSH151I
Temperature Range
D
-40°C, +125°C
•
D
SO8
(Plastic Micropackage)
PIN CONNECTIONS
(top view)
Offset Null 1
Inverting Input
Non-inverting Input
V
CC
1
2
3
4
8
Offset Null 2
7 V
CC
+
6
5
Output
N.C.
D =
Small Outline Package (SO) - also available in Tape & Reel (DT)
October 2000
1/6
TSH151
SCHEMATIC DIAGRAM
7 V
CC
+
non inverting
input
3
Internal
V
ref
6
output
2
inverting
input
1
Offset N1
8
C
c
Offset N2
4
V
CC
-
INPUT OFFSET VOLTAGE NULL CIRCUIT
TSH151
N1
N2
100k
W
V
CC
MAXIMUM RATINGS
Symbol
V
CC
V
id
V
i
I
in
T
oper
Supply Voltage
Differential Input Voltage
Input Voltage
Current On Offset Null Pins
Operating Free-Air Temperature range
Parameter
Value
±7
±5
±5
±20
-40 to +125
Unit
V
V
V
V
°C
OPERATING CONDITIONS
Symbol
V
CC
V
ic
Supply Voltage
Common Mode Input Voltage Range
Parameter
Value
±3 to ±6
V
CC
-
to V
CC
+
-3
Unit
V
V
2/6
TSH151
ELECTRICAL CHARACTERISTICS
V
CC
= ±5V, T
amb
= 25°C (unless otherwise specified)
Symbol
V
io
DV
io
I
ib
I
io
Parameter
Input Offset Voltage
T
min
.
≤
T
amb
≤
T
max
Input Offset Voltage Drift
T
min
.
≤
T
amb
≤
T
max.
Input Bias Current
.
Input Offset Current
.
Supply Current, no load
I
CC
T
min
.
≤
T
amb
≤
T
max
Avd
V
icm
CMR
SVR
V
CC
=
V
CC
=
V
CC
=
V
CC
=
±5V
±3V
±6V
±5V
800
300
200
-5 to +2
60
50
±3
±2.8
±2.9
±2.7
±50
±100
150
100
200
mA
MHz
V/µs
23
21
25
30
28
40
32
mA
Min.
Typ.
0.5
Max.
10
12
Unit
mV
µV/°C
300
200
pA
pA
10
2
2
Large Signal Voltage Gain Vo = ±2.5V
R
L
=
∝
R
L
= 100Ω
R
L
= 50Ω
Input Common Mode Voltage Range
Common-mode Rejection Ratio V
ic
= V
icm min.
Supply Voltage Rejection Ratio V
CC
= ±5V to ±3V
Output Voltage
R
L
= 100Ω
1300
850
650
-5.5 to +2.5
100
70
+3.5
-3.7
+3.3
-3.5
V/V
V
dB
dB
V
o
T
min
.
≤
T
amb
≤
T
max
I
o
GBP
SR
R
L
= 50Ω
R
L
= 100Ω
R
L
= 50Ω
V
Output Short Circuit Current Vid = ±1V, Vo = 0V
Gain Bandwidth Product
A
VCL
= 100, R
L
= 100Ω, C
L
= 15pF, f = 7.5MHz
Slew Rate V
in
= ±2V, A
VCL
= 1, R
L
= 100Ω, C
L
= 15pF
Equivalent Input Voltage Noise
R
s
= 50Ω
e
n
f
o
= 1kHz
f
o
= 1k0Hz
f
o
= 100kHz
f
o
= 1MHz
Overshoot V
in
= ±2V, A
VCL
= 1, R
L
= 100Ω, C
L
= 15pF
Settling Time 0.1%
1)
V
in
= ±1V, A
VCL
= -1
Rise and Fall Time (see note 1)
V
in
= ±100mV, A
VCL
= 2
Delay Time (see note 1)
V
in
= ±100mV, A
VCL
= 2
Phase Margin A
VM
= 1, R
L
= 100Ω, C
L
= 15pF
Total Harmonic Distortion
A
VCL
= 10, f = 1kHz, V
o
= ±2.5V, no load
Full Power Bandwidth
2)
Vo = 5Vpp, R
L
= 100Ω
Vo = 2Vpp, R
L
= 100Ω
SR
-------------------
-
Π
V
opp
20
18.2
18.1
18.2
10
70
5
4
45
0.02
13
32
nV/√Hz
K
ov
t
s
t
r
, t
f
t
d
φm
THD
%
ns
ns
ns
Degrees
%
FPB
MHz
1. See test waveform figure
2. Full power bandwidth =
3/6
TSH151
TEST WAVEFORM
EVALUATION CIRCUIT
+5V
10µF
50Ω
t
s
0.1% of edge amplitude
10nF
Input
50Ω
Output
1kΩ
10nF
90%
t
d
50%
t
r
V
in
10%
-5V
10µF
1kΩ
C
F
PRINTED CIRCUIT LAYOUT
As for any high frequency device, a few rules must
be observed when designing the PCB to get the
best performances from this high speed op amp.
From the most to the least important points :
u
Each power supply lead has to be by-
passed to ground with a 10nF ceramic ca-
pacitor very close to the device and a 10µF
tantalum capacitor.
u
To provide low inductance and low resist-
ance common return, use a ground plane
or common point return for power and sig-
nal.
u
All leads must be wide and as short as pos-
sible especially for op amp inputs. This is in
order to decrease parasitic capacitance
and inductance.
Use small resistor values to decrease time
constant with parasitic capacitance.
Choose component sizes as small as pos-
sible (SMD).
On output, decrease capacitor load so as
to avoid circuit stability being degraded
which may cause oscillation. You can also
add a serial resistor in order to minimise its
influence.
One can add in parallel with feedback re-
sistor a few pF ceramic capacitor C
F
adjust-
ed to optimize the settling time.
u
u
u
u
4/6
TSH151
MACROMODEL
Applies to: TSH151I
** Standard Linear Ics Macromodels, 1993.
** CONNECTIONS :
* 1 INVERTING INPUT
* 2 NON-INVERTING INPUT
* 3 OUTPUT
* 4 POSITIVEPOWER SUPPLY
* 5 NEGATIVE POWER SUPPLY
.SUBCKT TSH151 1 3 2 4 5 (analog)
********************************************************
.MODEL MDTH D IS=1E-8 KF=3.322525E-14
CJO=10F
* INPUT STAGE
RESD1 2 202 150
RESD2 1 201 150
CIP 202 5 10.000000E-12
CIN 201 5 10.000000E-12
EIP 10 5 202 5 1
EIN 16 5 201 5 1
RIP 10 11 2.600000E-01
RIN 15 16 2.600000E-01
RIS 11 15 1.683423E-01
DIP 11 12 MDTH 400E-12
DIN 15 14 MDTH 400E-12
VOFP 12 13 DC 0.000000E+00
VOFN 13 14 DC 0
IPOL 13 5 1.000000E-03
CPS 11 15 8E-09
DINN 17 13 MDTH 400E-12
ELECTRICAL CHARACTERISTICS
V
CC
= ±5V, T
amb
= 25°C (unless otherwise specificed)
Symbol
V
io
A
vd
I
CC
V
icm
V
OH
V
OL
I
sink
I
source
GBP
SR
φm
t
s
R
L
= 100Ω
R
L
= 100Ω
V
o
= 0V
V
o
= 0V
R
L
= 100Ω, C
L
= 15pF
R
L
= 100Ω, C
L
= 15pF
R
L
= 100Ω, C
L
= 15pF
A
v
= -1 at 0.1%
R
L
= 100Ω
No load
Conditions
Value
0
1.18
23
-5 to 2.5
+3.6
-3.6
108
108
130
172
25
40
Unit
mV
V/mV
mA
V
V
V
mA
mA
MHz
V/µs
Degrees
ns
5/6
VIN 17 5 1.500000e+00
DINR 15 18 MDTH 400E-12
VIP 4 18 5.000000E-01
FCP 4 5 VOFP 2.200000E+01
FCN 5 4 VOFN 2.200000E+01
* AMPLIFYING STAGE
FIP 5 19 VOFP 3.800000E+02
FIN 5 19 VOFN 3.800000E+02
RG1 19 5 1.455096E+03
RG2 19 4 1.455096E+03
CC 19 29 2.000000E-09
HZTP 29 30 VOFP 100
HZTN 30 5 VOFN 100
DOPM 19 22 MDTH 400E-12
DONM 21 19 MDTH 400E-12
HOPM 22 28 VOUT 5.000000E+02
VIPM 28 4 5.000000E+01
HONM 21 27 VOUT 5.000000E+02
VINM 5 27 5.000000E+01
EOUT 26 23 19 5 1
VOUT 23 5 0
ROUT 26 3 9.978126E+00
COUT 3 5 1.000000E-13
DOP 19 25 MDTH 400E-12
VOP 4 25 1.946965E+00
DON 24 19 MDTH 400E-12
VON 24 5 1.946965E+00
.ENDS
FPGA/CPLD
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