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IDT74FCT163501/A/C
3.3V CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGES
3.3V CMOS 18-BIT
REGISTERED TRANSCEIVER
IDT74FCT163501/A/C
FEATURES:
−
−
−
−
−
−
−
−
−
0.5 MICRON CMOS Technology
Typical t
SK
(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
V
CC
= 3.3V ±0.3V, Normal Range or V
CC
= 2.7V to 3.6V, Extended
Range
CMOS power levels (0.4µ W typ. static)
Rail-to-Rail output swing for increased noise margin
Low Ground Bounce (0.3V typ.)
Inputs (except I/O) can be driven by 3.3V or 5V components
Available in SSOP, TSSOP and TVSOP Packages
DESCRIPTION:
The FCT163501/A/C 18-bit registered transceivers are built using
advanced dual metal CMOS technology. These high-speed, low-power
18-bit registered bus transceivers combine D-type latches and D-type flip-
flops to allow data flow in transparent, latched and clocked modes. Data flow
in each direction is controlled by output-enable (OEAB and
OEBA),
latch
enable (LEAB and LEBA) and clock (CLKAB and CLKBA) inputs. For A-
to-B data flow, the device operates in transparent mode when LEAB is high.
When LEAB is low, the A data is latched if CLKAB is held at a high or low
logic level. If LEAB is low, the A bus data is stored in the latch/flip-flop on
the low-to-high transition of CLKAB. OEAB performs the output enable
function on the B port. Data flow from B port to A port is similiar but requires
using
OEBA,
LEBA and CLKBA. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for improved noise
margin.
The FCT163501/A/C have series current limiting resistors. These offer
low ground bounce, minimal undershoot, and controlled output fall times-
reducing the need for external series terminating resistors.
FUNCTIONAL BLOCK DIAGRAM
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
1
30
28
27
55
2
C
A
1
3
C
D
54
D
B
1
C
D
C
D
TO 17 OTHER CHANNELS
INDUSTRIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
JUNE 2000
DSC-2776/5
IDT74FCT163501/A/C
3.3V CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
OEA B
LEAB
A
1
GND
A
2
A
3
V
CC
A
4
A
5
A
6
GND
A
7
A
8
A
9
A
10
A
11
A
12
GND
A
13
A
14
A
15
V
CC
A
16
A
17
GND
A
18
OEB A
LEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SO56-1
SO56-2
SO56-3
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
CLKAB
B
1
GND
B
2
B
3
V
CC
B
4
B
5
B
6
GND
B
7
B
8
B
9
B
10
B
11
B
12
GND
B
13
B
14
B
15
V
CC
B
16
B
17
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM(2)
V
TERM(3)
V
TERM(4)
T
STG
I
OUT
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to +4.6
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +60
Unit
V
V
V
°C
mA
3v16-link
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. Input terminals.
4. Outputs and I/O terminals.
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3.5
3.5
Max.
6
8
Unit
pF
pF
3v16-link
NOTE:
1. This parameter is measured at characterization but not tested.
FUNCTION TABLE
(1,4)
Inputs
OEAB
LEAB
X
H
H
L
L
L
L
CLKAB
X
X
X
↑
↑
L
H
Ax
X
L
H
L
H
X
X
L
H
H
H
H
H
H
Outputs
Bx
Z
L
H
L
H
B
(2)
B
(3)
GND
B
18
CLKBA
GND
SSOP/ TSSOP/ TVSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
OEAB
OEBA
LEAB
LEBA
CLKAB
CLKBA
Ax
Bx
Description
A-to-B Output Enable Input
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
B-to-A Latch Enable Input
A-to-B Clock Input
B-to-A Clock Input
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar but uses
OEBA,
LEBA, and CLKBA.
2. Output level before the indicated steady-state input conditions were
established.
3. Output level before the indicated steady-state input conditions were
established, provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
↑
= LOW-to-HIGH Transition
2
IDT74FCT163501/A/C
3.3V CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40°C to +85°C, V
CC
= 2.7V to 3.6V
Symbol
V
IH
V
IL
I
I H
I
I L
I
OZH
I
OZL
V
IK
I
ODH
I
ODL
V
OH
Parameter
Input HIGH Level (Input pins)
Input HIGH Level (I/O pins)
Input LOW Level
(Input and I/O pins)
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
Input LOW Current (Input pins)
Input LOW Current (I/O pins)
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Output HIGH Current
Output LOW Current
Output HIGH Voltage
V
CC
= Min., I
IN
= –18mA
V
CC
= 3.3V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
(3)
V
CC
= 3.3V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= 3V
V
IN
= V
IH
or V
IL
V
OL
Output LOW Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= 3V
V
IN
= V
IH
or V
IL
I
OS
V
H
I
CCL
I
CCH
I
CCZ
Short Circuit Current
(4)
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max.
V
IN
= GND or V
CC
V
CC
= Max., V
O
= GND
(3)
—
–60
—
—
–135
150
0.1
–240
—
10
mA
mV
µA
I
OL
= 0.1mA
I
OL
= 16mA
I
OL
= 24mA
I
OL
= 24mA
—
—
—
—
0.2
0.3
0.3
0.2
0.4
0.55
0.5
V
I
OH
= –0.1mA
I
OH
= –3mA
I
OH
= –8mA
V
CC
= Max.
V
CC
= Max.
V
I
= 5.5V
V
I
= V
CC
V
I
= GND
V
I
= GND
V
O
= V
CC
V
O
= GND
—
—
—
—
—
—
—
–36
50
V
CC
–0.2
2.4
2.4
(5)
—
—
—
—
—
—
–0.7
–60
90
—
3
3
±1
±1
±1
±1
±1
±1
–1.2
–110
200
—
—
—
V
mA
mA
V
µA
µA
Guaranteed Logic LOW Level
Test Conditions
(1)
Guaranteed Logic HIGH Level
Min.
2
2
–0.5
Typ.
(2)
—
—
—
Max.
5.5
Vcc+0.5
0.8
V
Unit
V
3v16-link
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. V
OH
= Vcc -0.6V at rated current.
3
IDT74FCT163501/A/C
3.3V CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
V
CC
= Max.
Test Conditions
(1)
V
IN
= V
CC
– 0.6V
(3)
V
IN
= V
CC
V
IN
= GND
Min.
—
—
Typ.
(2)
2
60
Max.
30
100
Unit
µA
µ A/
MHz
V
CC
= Max.
Outputs Open
OEAB =
OEBA
= V
CC
or GND
50% Duty Cycle
One Input Toggling
V
CC
= Max.
Outputs Open
f
CP
= 10MHz (CLKAB)
50% Duty Cycle
OEAB =
OEBA
= V
CC
LEAB = GND
fi = 5MHz
50% Duty Cycle
One Bit Toggling
V
CC
= Max.
Outputs Open
f
CP
= 10MHz (CLKAB)
50% Duty Cycle
OEAB =
OEBA
= V
CC
LEAB = GND
fi = 2.5MHz
50% Duty Cycle
Eighteen Bits Toggling
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
—
0.6
1
mA
V
IN
= V
CC
–0.6V
V
IN
= GND
—
0.6
1
V
IN
= V
CC
V
IN
= GND
—
3
5
(5)
V
IN
= V
CC
–0.6V
V
IN
= GND
—
3
5.3
(5)
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + fiNi)
I
CC
= Quiescent Current (I
CCL,
I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
i
= Input Frequency
N
i
= Number of Inputs at fi
4
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