CMOS STATIC RAM
256K (64K x 4-BIT)
Integrated Device Technology, Inc.
IDT61298SA
FEATURES:
• 64K x 4 high-speed static RAM
• Fast Output Enable (
OE
) pin available for added system
flexibility
• High speed (equal access and cycle times)
— Commercial: 12/15 ns (max.)
• JEDEC standard pinout
• 300 mil 28-pin SOJ
• Produced with advanced CMOS technology
• Bidirectional data inputs and outputs
• Inputs/Outputs TTL-compatible
• Three-state outputs
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The lDT61298SA is a 262,144-bit high-speed static RAM
organized as 64K x 4. It is fabricated using IDT’s high-
performance, high-reliability CMOS technology. This state-of-
the-art technology, combined with innovative circuit design
techniques, provides a cost-effective approach for memory
intensive applications.
The IDT61298SA features two memory control functions:
Chip Select (
CS
) and Output Enable (
OE
). These two func-
tions greatly enhance the IDT61298SA's overall flexibility in
high-speed memory applications.
Access times as fast as 12ns are available. The IDT61298SA
offers a reduced power standby mode, I
SB1
, which enables
the designer to considerably reduce device power require-
ments. This capability significantly decreases system power
and cooling levels, while greatly enhancing system reliability.
All inputs and outputs are TTL-compatible and the device
operates from a single 5 volt supply. Fully static asynchronous
FUNCTIONAL BLOCK DIAGRAM
A
0
V
CC
D
E
C
O
D
E
R
A
15
GND
262,144-BIT
MEMORY ARRAY
I/O
0
I/O
1
I/O
2
I/O
3
I/O CONTROL
INPUT
DATA
CONTROL
CS
WE
OE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2971 drw 01
COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
MAY 1996
DSC-2971/6
7.1
1
IDT61298SA
CMOS STATIC RAM 256K (64K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (Continued)
circuitry, along with matching access and cycle times, favor
the simplified system design approach.
The IDT61298SA is packaged in a 300 mil, 28-pin SOJ,
providing improved board-level packing densities.
TRUTH TABLE
(1,2)
CS
L
L
L
H
V
HC
(3)
OE
L
X
H
X
X
WE
H
L
H
X
X
I/O
DATA
OUT
DATA
IN
High-Z
High-Z
High-Z
Function
Read Data
Write Data
Outputs Disabled
Deselected - Standby (I
SB
)
Deselected - Standby (I
SB1
)
2971 tbl 01
NOTES:
1. H = V
IH
, L = V
IL
, x = Don't care.
2. V
LC
= 0.2V, V
HC
= V
CC
-0.2V.
3. Other inputs
≥V
HC
or
≤V
LC
.
PIN CONFIGURATION
NC
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
CC
A
15
A
14
A
13
A
12
A
11
A
10
NC
NC
I/O
3
I/O
2
I/O
1
I/O
0
Rating
Terminal Voltage
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
Power Dissipation
DC Output
Current
Com’l.
–0.5 to +7.0
Unit
V
V
TERM
(2)
T
A
T
BIAS
T
STG
P
T
I
OUT
0 to +70
–55 to +125
–55 to +125
1.0
50
°C
°C
°C
W
mA
SO28-5
21
20
19
18
17
16
15
GND
CS
OE
WE
2971 drw 02
SOJ
TOP VIEW
NOTES:
2971 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
CC
+ 0.5V.
PIN DESCRIPTIONS
Name
A
0
–A
14
I/O
0
–I/O
7
Description
Addresses
Data Input/Output
Chip Select
Write Enable
Output Enable
Ground
Power
2971 tbl 04
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz, SOJ Package)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
5
7
Unit
pF
pF
CS
WE
OE
GND
V
CC
NOTE:
2971 tbl 03
1. This parameter is determined by device characterization, but is not
production tested.
7.1
2
IDT61298SA
CMOS STATIC RAM 256K (64K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Commercial
Temperature
0°C to +70°C
GND
0V
Vcc
5V
±
10%
2971 tbl 05
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Min.
4.5
0
2.2
Typ.
5.0
0
—
—
Max.
5.5
0
V
CC
+ 0.5V
0.8
Unit
V
V
V
V
Input Low Voltage –0.5
(1)
NOTE:
2971 tbl 06
1. V
IL
(min.) = –1.5V for pulse width less than 10ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS
(1)
(V
CC
= 5V
±
10%, V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
61298SA12
Symbol
I
CC
Parameter
Dynamic Operating Current
CS
= V
IL
, Outputs Open
V
CC
= Max., f = f
MAX(2)
Standby Power Supply
Current (TTL Level)
CS
≥
V
IH
, V
CC
= Max.,
Outputs Open, f = f
MAX(2)
Full Standby Power
Supply Current (CMOS Level)
CS
≥
V
HC
, V
CC
= Max.,
f = 0
(2)
, V
LC
≥
V
IN
≥
V
HC
Com’l.
Mil.
61298SA15
Com’l.
Mil.
Unit
mA
160
—
140
—
I
SB
50
—
45
—
mA
I
SB1
20
—
20
—
mA
NOTES:
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
); f = 0 means no address input lines are changing.
2971 tbl 07
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
2971 tbl 08
5V
480
Ω
DATA
OUT
255
Ω
30pF*
DATA
OUT
255Ω
5V
480Ω
5pF*
2971 drw 03
2971 drw 04
Figure 1. AC Test Load
*Includes scope and jig capacitances
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW
, t
WHZ
)
7.1
3
IDT61298SA
CMOS STATIC RAM 256K (64K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
V
CC
= 5.0V
±
10%
IDT61298SA
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Condition
V
CC
= Max.,
V
IN
= GND to V
CC
V
CC
= Max.,
CS
= V
IH,
V
OUT
= GND to V
CC
I
OL
= 8mA, V
CC
= Min.
I
OL
= 10mA, V
CC
= Min.
I
OH
= –4mA, V
CC
= Min.
Min.
—
—
—
—
2.4
Typ
.
—
—
—
—
—
Max.
5
µA
5
0.4
0.5
—
V
V
2971 tbl 09
Unit
µA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
10%)
61298SA12
Symbol
Read Cycle
t
RC
t
AA
t
ACS
t
CLZ
t
OE
t
OLZ
(1)
t
OHZ
t
OH
t
PU
(1)
t
PD
(1)
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
DW
t
DH
t
WHZ
(1)
t
OW
(1)
(1)
(1)
61298SA15
Min.
15
—
—
4
—
—
0
—
3
0
—
15
10
10
0
10
0
7
0
—
4
Max.
—
15
15
—
7
7
—
6
—
—
15
—
—
—
—
—
—
—
—
6
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2971 tbl 10
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power-Up Time
Chip Deselect to Power-Down Time
Write Cycle Time
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Data Hold Time
Write Enable to Output in High-Z
Output Active from End-of-Write
Min.
12
—
—
4
—
—
0
—
3
0
—
12
9
9
0
9
0
6
0
—
4
Max.
—
12
12
—
6
6
—
6
—
—
12
—
—
—
—
—
—
—
—
6
—
t
CHZ
(1)
Write Cycle
NOTES:
1. This parameter is guaranteed with AC test load (Figure 2) by device characterization, but is not production tested.
7.1
4
IDT61298SA
CMOS STATIC RAM 256K (64K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1
(1)
t
RC
ADDRESS
t
AA
t
OH
OE
t
OLZ
t
OE
(5)
t
OHZ
(5)
CS
t
ACS
t
CLZ
DATA
OUT
(5)
t
CHZ
DATA VALID
(5)
2971 drw 05
TIMING WAVEFORM OF READ CYCLE NO. 2
(1,2,4)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
DATA VALID
2971 drw 06
t
OH
TIMING WAVEFORM OF READ CYCLE NO. 3
(1,3,4)
CS
t
ACS
t
CLZ (5)
DATA
OUT
t
PU
V
CC
I
CC
SUPPLY
CURRENT I
SB
2971 drw 07
t
CHZ
DATA VALID
t
PD
(5)
NOTES:
1.
WE
is HIGH for Read cycle.
2. Device is continuously selected,
CS
is LOW.
3. Address valid prior to or coincident with
CS
transition LOW.
4.
OE
is LOW.
5. Transition is measured
±200mV
from steady state.
7.1
5
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