Latch-up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Ambient Temperature
[2]
0
°
C to +70
°
C
V
CC
5V
±
10%
Electrical Characteristics
Over the Operating Range
[3]
-12
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
GND < V
I
< V
CC
Output Leakage Current GND < V
O
< V
CC
, Output
Disabled
V
CC
Operating Supply
Current
Automatic CE
Power-down Current—
TTL Inputs
Automatic CE
Power-down Current—
CMOS Inputs
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Com’l
L
30
Test Conditions
V
CC
= Min., I
OH
=–4.0 mA
V
CC
= Min., I
OL
=8.0 mA
2.2
–0.5
–5
–5
Min.
2.4
0.4
V
CC
+
0.3V
0.8
+5
+5
160
2.2
–0.5
–5
–5
Max.
Min.
2.4
0.4
V
CC
+
0.3V
0.8
+5
+5
155
90
30
5
10
10
0.05
10
30
2.2
–0.5
–5
–5
-15
Max.
Min.
2.4
0.4
V
CC
+
0.3V
0.8
+5
+5
150
-20
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
mA
I
SB1
Max. V
CC
, CE > V
IH
, Com’l
V
IN
> V
IH
or
L
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
Com’l
CE > V
CC
– 0.3V L
V
IN
> V
CC
– 0.3V
or V
IN
< 0.3V, f = 0
I
SB2
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
Document #: 38-05160 Rev. *B
Page 2 of 11
CY7C199
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
8
8
Unit
pF
pF
AC Test Loads and Waveforms
[5]
R1 481Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
R2
255
Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
255Ω
3.0V
10%
GND
≤t
r
R1 481Ω
ALL INPUT PULSES
90%
90%
10%
≤t
r
(a)
(b)
THÉVENIN EQUIVALENT
167
Ω
1.73V
OUTPUT
Data Retention Characteristics
Over the Operating Range (L-version only)
Parameter
V
DR
I
CCDR
t
CDR[4]
t
R [5]
Description
V
CC
for Data Retention
Data Retention Current
V
CC
= V
DR
= 2.0V,
CE > V
CC
– 0.3V,
Chip Deselect to Data Retention Time V > V – 0.3V or V < 0.3V
IN
CC
IN
Operation Recovery Time
Conditions
[6]
Min.
2.0
10
0
200
Max.
Unit
V
µA
ns
µs
Data Retention Waveform
DATA RETENTION MODE
V
CC
3.0V
t
CDR
CE
Notes:
4. Tested initially and after any design or process changes that may affect these parameters.
5. t
R
< 3 ns for the -12 and the -15 speeds. t
R
< 5 ns for the -20 and slower speeds.
6. No input may exceed V
CC
+ 0.5V.
V
DR
> 2V
3.0V
t
R
Document #: 38-05160 Rev. *B
Page 3 of 11
CY7C199
Switching Characteristics
Over the Operating Range
[3,7]
-12
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[10, 11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
[9]
WE HIGH to Low-Z
[8]
3
12
9
9
0
0
8
8
0
7
3
15
10
10
0
0
9
9
0
7
3
20
15
15
0
0
15
10
0
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to
Low-Z
[8]
0
5
3
5
0
12
0
15
3
7
0
20
OE HIGH to High-Z
[8, 9]
CE LOW to Low-Z
[8]
CE HIGH to High-Z
[8, 9]
CE LOW to Power-up
CE HIGH to Power-down
3
12
5
0
7
3
9
12
12
3
15
7
0
9
15
15
3
20
9
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
-15
Max.
Min.
-20
Max.
Unit
Notes:
7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V, and output loading of the specified I
OL
/I
OH
and 30-pF load capacitance.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a
write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
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