MOTOROLA
Order this document
by MC16S044T3B/D
SEMICONDUCTOR
TECHNICAL DATA
2 x 2M x 4
Product Preview
16M Synchronous DRAM
Family
x4, x8, x16
The family of 16M Synchronous Dynamic RAMs is fabricated using 0.45µ
CMOS high–speed silicon gate process technology. It includes devices
organized as 2 banks x 2,097,152 words x 4 bits, 2 banks x 1,048,576 words
x 8 bits, and 2 banks x 524,288 words x 16 bits. Advanced circuit design and
fine line processing provide high performance, improved reliability, and low
cost.
Fully synchronous operations are referenced to the rising edge of the clock
input and can achieve data transfer rates up to 100 MHz. These devices are
ideal for main memory in applications such as workstations, microcomputers,
and refresh memory in CRTs.
These devices are packaged in a standard 400 mil thin small outline
package (TSOP).
•
Single 3.3 V
±
0.3 V Power Supply
•
Clock Frequency 100 MHz/83 MHz
•
Fully Synchronous Operation Referenced to Clock Rising Edge
•
Dual Bank Operation Controlled by Bank Address (BA)
•
CAS Latency Programmable to 1/2/3
•
Burst Length Programmable to 1/2/4/8/Page
•
Burst Type Programmable to Sequential/Interleaved
•
Auto Precharge: All Bank Precharge Controlled by A10 and BA
•
Auto–Refresh and Self–Refresh
•
4096 Refresh Cycles: 64 ms
•
LVTTL Interface
•
Package:
MC16S044T3B: 400 mil, 44–Pin TSOP (0.8 mm Pitch)
MC16S084T3B: 400 mil, 44–Pin TSOP (0.8 mm Pitch)
M116S163AST: 400 mil, 50–Pin TSOP (0.8 mm Pitch)
MC16S044T3B
2 x 1M x 8
MC16S084T3B
T PACKAGE
400 MIL TSOP
CASE 924B–01
2 x 512K x 16
M116S163AST
T PACKAGE
400 MIL TSOP
CASE 985C–01
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 1
4/4/97
©
Motorola, Inc. 1997
MOTOROLA DRAM
MC16S044T3B•MC16S084T3B•M116S163AST
1
PIN ASSIGNMENTS
400 MIL TSOP
44–PIN
VCC
NC
VSSQ
DQ0
VCCQ
NC
VSSQ
DQ1
VCCQ
NC
NC
WE
CAS
RAS
CS
BA
A10
A0
A1
A2
A3
VCC
VCC
DQ0
VSSQ
DQ1
VCCQ
DQ2
VSSQ
DQ3
VCCQ
NC
NC
WE
CAS
RAS
CS
BA
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VSS
DQ7
VSSQ
DQ6
VCCQ
DQ5
VSSQ
DQ4
VCCQ
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
VSS
NC
VSSQ
DQ3
VCCQ
NC
VSSQ
DQ2
VCCQ
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
VCC
DQ0
DQ1
VSSQ
DQ2
DQ3
VCCQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VCCQ
LDQM
WE
CAS
RAS
CS
BA
A10
A0
A1
A2
A3
400 MIL TSOP
50–PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VCCQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VCCQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
x8
x4
VCC
x16
PIN NAMES
A0 – A10 . . . . . . . . . . . . . . . . . Address Inputs
BA . . . . . . . . . . . . . . . . . . . . . . . Bank Address
CS . . . . . . . . . . . . . . . . . . . . . . . . . Chip Select
CAS . . . . . . . . . . . . . . Column Address Strobe
DQ0 – DQ15 . . . . . . . . . . . . Data Input/Output
RAS . . . . . . . . . . . . . . . . Row Address Strobe
WE . . . . . . . . . . . . . . . . . . . . . . . . Write Enable
CKE . . . . . . . . . . . . . . . . . . . . . . . Clock Enable
CLK . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input
DQM (x4, x8) . . . Output Disable/Write Mask
UDQM/ . . . . . . . . Output Disable/Write Mask
LDQM (x16)
(Upper/Lower Byte)
VCC . . . . . . . . . . . . . . . . . . . . . Power (+ 3.3 V)
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
VCCQ . . . . . . Power (+ 3.3 V) (for I/O Buffer)
VSSQ . . . . . . . . . . . . . Ground (for I/O Buffer)
NC . . . . . . . . . . . . . . . . . . . . . . . No Connection
MC16S044T3B•MC16S084T3B•M116S163AST
2
MOTOROLA DRAM
BLOCK DIAGRAM
CLK
CLOCK
BUFFER
CKE
CS
RAS
CAS
WE
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
ROW DECODER
COLUMN DECODER
2048 x 512 x 8*
CELL ARRAY
BANK 0
SENSE AMPLIFIER
A10
MODE
REGISTER
A0 – A9,
BA
ADDRESS
BUFFER
DATA CONTROL
CIRCUIT
DQ
BUFFER
DQ0 – DQ7*
DQM
ROW DECODER
REFRESH
COUNTER
COLUMN
COUNTER
SENSE AMPLIFIER
2048 x 512 x 8*
CELL ARRAY
BANK 1
COLUMN DECODER
* This figure is for the MC16S084T3B (2 x 1M x 8) device.
Refer to the following table for differences in addressing, array size, and DQ width.
Row
Address
A0 – A10
A0 – A10
A0 – A10
Column
Address
A0 – A9
A0 – A8
A0 – A7
Device
MC16S044T3B
MC16S084T3B
M116S163AST
Array Size
2048 x 1024 x 4
2048 x 512 x 8
2048 x 256 x 16
DQ Width
DQ0 – DQ3
DQ0 – DQ7
DQ0 – DQ15
MOTOROLA DRAM
MC16S044T3B•MC16S084T3B•M116S163AST
3
ABSOLUTE MAXIMUM RATINGS
(See Note)
Rating
Power Supply Voltage (to VSS)
Power Supply Voltage for Output
(to VSSQ)
Input Voltage (Relative to VSS)
Output Voltage (Relative to VSSQ)
Output Current
Power Dissipation
Operating Temperature Range
Storage Temperature Range
Symbol
VCC
VCCQ
Vin
Vout
Iout
PD
TA
Tstg
Value
– 0.3 to + 4.6
– 0.3 to + 4.6
– 0.3 to + 4.6
– 0.3 to + 4.6
50
1000
0 to + 70
– 55 to + 150
Unit
V
V
V
V
mA
mW
°C
°C
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 3.3 V
±
0.3 V, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(All Voltages Referenced to VSS)
Parameter
Supply Voltage (Operating Voltage Range)
Symbol
VCC
VSS
Supply Voltage for Output (Operating Voltage Range)
VCCQ
VSSQ
Logic High Voltage, All Inputs
Logic Low Voltage, All Inputs
High Level Output Voltage (IOH = – 2 mA)
Low Level Output Voltage (IOL = 2 mA)
Input Leakage Current (0 V
≤
Vin < VCC, All Other Pins Not Under
Test = 0 V)
Output Leakage Current (0 V
≤
Vout < VCC, Output Disable)
VIH
VIL
VOH
VOL
Ilkg(1)
Ilkg(0)
Min
3.0
0
3.0
0
2.0
– 0.3
2.4
—
–5
–5
Typ
3.3
0
3.3
0
—
—
—
—
—
—
Max
3.6
0
3.6
0
VCC + 0.3
0.8
—
0.4
5
5
V
V
V
V
µA
µA
V
Unit
V
NOTE: VIH (Max) = VCC/VCCQ + 1.2 V for pulse width
≤
5 ns. VIL (Min) = VSS/VSSQ – 1.2 V for pulse width
≤
5 ns.
CAPACITANCE
(f = 1.0 MHz @ 25 mV rms, VDD = VDDQ = 3.3 V
±
0.3 V, VSS = VSSQ = 0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance
All Non–CLK Inputs
CLK
I/O Capacitance
DQ0 – DQ15
CI/O
Symbol
Cin
Max
4
6
5
pF
Unit
pF
NOTE: Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = I
∆t/∆V.
MC16S044T3B•MC16S084T3B•M116S163AST
4
MOTOROLA DRAM
AVERAGE SUPPLY CURRENT
Max (x4 / x8 / x16)
Characteristic
Ch
i i
Operating Current
tRC = Min tCLK = Min
Min,
Standby Current
Both Banks Idle tCLK = Min
Idle,
Single Bank
Dual Bank Interleaved
Clock Enabled (CKE = H)
Clock Disabled (CKE = L)
(Power Down Mode)
Clock Enabled (CKE = H)
Clock Disabled (CKE = L)
(Power Down Mode)
Clock Enabled (CKE = H)
Clock Disabled (CKE = L)
(Power Down Mode)
Read Cycle
Write Cycle
Symbol
S b l
ICC1
ICC1B
ICC2
ICC2P
ICC2S
ICC2PS
ICC3
ICC3P
ICC4R
ICC4W
ICC5
ICC6
–10
90
130
30
2
13
2
75
3
135
125
65
2
–12
80
115
28
2
13
2
70
3
125
115
60
2
Unit
U i
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1, 2
1
1
2
Notes
N
1
1
1
Standby Current
Both Banks Idle CLK = L
Idle,
Active Standby Current
Both Banks Active tCLK = Min CS = H
Active,
Min,
Burst Current
Both Banks Active tCLK = Min
Active,
Auto–Refresh Current
tRC = Min, tCLK = Min
Self–Refresh Current
CKE = 0.2 V
NOTES:
1. These parameters depend on the specified cycle rate and are measured at minimum tCK and tRC. Input signals are changed one time
during CLK.
2. These parameters depend on output loading. Specified values are obtained with the output open.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = VCCQ = 3.3 V
±
0.3 V, VSS = VSSQ = 0 V, VIL = 0.4 V, VIH = 2.0 V,
TA = 0 to 70°C, Input and Output Timing Reference Level = 1.4 V, Unless Otherwise Noted)
ALL DEVICES: READ, WRITE, AND READ–WRITE CYCLES
(See Notes 1, 2, 3, and 4)
–10
Parameter
P
Clock Cycle Time
(CL = 1)
(CL = 2)
(CL = 3)
Symbol
S b l
tCLK
Min
30
15
10
3
3
1
3
1
3
Max
1000
1000
1000
—
—
10
—
—
—
Min
36
18
12
4
4
1
3
1
3
–12
Max
1000
1000
1000
—
—
10
—
—
—
Unit
U i
ns
Notes
N
Clock High Pulse Width
Clock Low Pulse Width
Transition Time of CLK
Data Input Setup Time
Data Input Hold Time
Address Setup Time
tCH
tCL
tT
tDS
tDH
tAS
ns
ns
ns
ns
ns
ns
5
NOTES:
1. See Figure 1 for input and output reference levels and output load conditions.
2. Transition time (rise and fall) of input signals is 2 ns.
3. Transition times are measured between VIH and VIL. Transition times (rise and fall) of input signals are fixed slope.
4. Power up must be performed in the following sequence:
(1) With the device in the no–operation state, simultaneously apply power to VCC and VCCQ, and start the CLK signal.
(2) Pause for a minimum of 200
µs.
(3) Set DQM and CKE signals to VIH to ensure high impedance at the DQ outputs.
(4) Precharge both banks.
(5) Initialize the mode register with the mode register set command.
(6) Issue a minimum of eight auto–refresh dummy commands to stabilize the internal device circuitry.
Steps 5 and 6 may be interchanged.
5. tCH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (Min). tCL is the pulse width of CLK
measured from the negative edge to the positive edge referenced to VIL (Max).
MOTOROLA DRAM
MC16S044T3B•MC16S084T3B•M116S163AST
5
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