SM3G
ULTRA MINIATURE
STRATUM 3 MODULE
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630- 851- 4722
Fax: 630- 851- 5040
www.conwin.com
Application
The SM3G Timing Module is a
complete system clock module for
Stratum 3 timing applications and
conforms to GR-1244-CORE (Issue
2), GR-253-CORE (Issue 3), ITU-T
G.812 (Type 3) and ITU-T G813 (Option
2). Applications include shared port
adapters, data digital cross connects,
ADM’s, DSLAM’s, multiservice platforms,
switches and routers in TDM, SDH and
SONET environments.
The SM3G Timing Module helps
reduce the cost of your design by
minimizing your development time and
maximizing your control of the system
clock with our simplified design.
This product is compliant with all
required ROHS specifications.
Bulletin
Page
Revision
Date
Issued By
Features
•
Small Package Size, 1.45 x 1.0 x
0.25 inches
•
Four Auto Select Input
References, 8 kHz - 77.76 MHz
•
Frequency Qualification and Loss
of Reference detection for each
input
•
Hitless Reference Switching
•
Master/Slave Operation with
Phase Adjustment
•
Manual/Autonomous Operation
•
Bi-Directional SPI Port Control
•
Three CMOS Frequency Outputs
- Output1 from 12.96 - 77.76
MHz, M/S Output @ 8kHz, BITS
@2.048 MHz or 1.544 MHz
•
3.3V operation
•
ROHS Compliant
TM083
1 of 36
03
11 Feb 10
ENG
General Description
The SM3G timing module provides a clock output that meets or exceeds Stratum 3 specifications given in GR-1244-CORE (Issue
2), GR-253-CORE (Issue 3), ITU-T G.812 (Type 3) and ITU-T G813 (Option 2). The SM3G features four reference inputs that will
auto-detect the following reference frequencies: 8 kHz, 1.544 MHz, 2.048 MHz, 12.96 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84
MHz and 77.76 MHz.
The SM3G timing module can be configured during production to produce an output up to 77.76 MHz. This output is derived from
an onboard VCXO and must be specified when ordering. The BITS output selectable for either 1.544 or 2.048 MHz. The master/slave
output is 8KHz. The user communicates with the SM3G module through a SPI port. The user controls the SM3G operation by writing
to the appropriate registers. The user can also enable or disable SPI operation through a SPI_Enable pin.
The SM3G offers a wide range of options for the system designer. The bandwidth is SPI Port-selectable from 0.025 Hz to 1.6 Hz.
0.098 Hz is the recommended operational bandwidth for SONET Minimum Clock and most Stratum 3 applications. The 8 kHz output
has an adjustable pulse width. The pull-in range is also adjustable to establish the desired reference frequency rejection limits. A
Free Run frequency calibration value can be written to the module to provide a high degree of accuracy in the free run mode. The
reference frequency for any given reference input is automatically detected. A wealth of status information is available through the SPI
Port registers. The user also has a choice between autonomous or full manual control operation.
In manual mode, the user controls the module operating modes Free Run, Hold Over or locked to a specific reference in normal
mode. If the chosen reference is unavailable or disqualified the module automatically enters Hold Over.
In autonomous control mode, operational mode selection occurs automatically based on reference priority and qualification status.
When the active reference becomes disqualified, the module will switch to another qualified reference. If none is available, it will switch
to Holdover. In the revertive mode the module will seek to acquire the highest priority qualified reference. In the non-revertive mode
the module will not return to the previous reference even after it is re-qualified unless there are no other qualified references.
Switching between references is hitless. Likewise, the output frequency slew rate is minimized during any change of operating
mode, including entry into and return from Free Run or Hold Over to protect traffic from transient-induced bit errors.
Reference Status information and the operating mode information is accessed through status registers. The module will set the
Interrupt pin (SPI_INT) low to indicate a status change. An Alarm pin is used to indicate failure of the active reference status.
Free Run operation guarantees an output within 4.6ppm of nominal frequency and Holdover operation guarantees the output
frequency will not change by more than 0.37ppm during the first 24 hours. Frequency accuracy is based on a TCXO for its small size,
low power consumption and outstanding performance over all environmental conditions.
The module operates on 3.3V ± 5% with a typical power draw of less than 500 milliwatts. The module operates over the 0° to 70° C
commercial temperature range.
Functional Block Diagram
Figure 1
TRST
TCK
TDO
TDI
TMS
M/S REF
REF 1 - 4
RESET
MASTER SELECT
T1/E1
SPI_ENBL
SPI_CLK
SPI_IN
SPI_OUT
SPI_INT
Bus Interface
Reference Priority,
Revertivity and Mask
Table
4
Control
Mode
Reference
Selection
DPLL
APLL
LOS
LOL
HOLD_GOOD
Reference Input Monitor
OCXO
EEPROM
DAC
VCXO
OUTPUT1
M/S_OUT
BITS_CLK
Data Sheet #:
TM083
Page 2
of
36
Rev:
03
Date:
02/11/10
© Copyright 2010 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Specifications for Ultra Miniature Stratum 3
Table 1
Parameter
Voltage
Power
Operating Temp Range
Reference Frequency 1, 2, 3, 4
CMOS Output Frequency #1
M/S Output
BITS_Clk
Master/Slave Input Reference
Input Reference Pulse Width
Reference Qualification Time
Input Capacitance (LVCMOS)
Output Drive Levels (LVCMOS)
Free Run Accuracy
Hold Over Accuracy
Dimensions
Specification
3.3V ± 5%
< 500 mW
0° - 70°C
8 kHz - 77.76 MHz (Auto Detected)
12.96 MHz - 77.76 MHz
8 kHz
1.544/2.048 MHz (Selectable)
8 kHz - 77.76 MHz
10 ns Min @ 8 kHz, 5 ns Min @ >8 kHz
10 sec.
10 pF
Source Current: 7 mA, Sink Current: 10 mA
4.6 ppm
0.37 ppm
1.45 x 1.0 x 0.25 inches (36.83 x 25.4 x 6.35 mm)
Pin Description
Table 2
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I/O
O
O
I
I
I
I
I
Pin Name
LOS
LOL
M/S Ref
REF1
REF2
REF3
REF4
TDI
TMS
TRST
BITS_CLK
M/S_OUT
OUTPUT1
VPP
VPN
T1/E1
HOLD_GOOD
TDO
TCK
GND
SPI_CLK
SPI_IN
VCC
SPI_ENBL
RESET
SPI_OUT
SPI_INT
MASTER SELECT
Pin Description
Alarm Output - Loss of Active Reference Signal
Alarm Output - Loss of Lock
Master/Slave reference input – 8 kHz to 77.76 MHz auto detected
Reference Input 1 – 8 kHz to 77.76 MHz auto detected
Reference Input 2 – 8 kHz to 77.76 MHz auto detected
Reference Input 3 – 8 kHz to 77.76 MHz auto detected
Reference Input 4 – 8 kHz to 77.76 MHz auto detected
JTAG TDI pin
JTAG TMS pin
JTAG TRST pin
1.544 or 2.048 MHz output selected by pin 16
Master/Slave 8 kHz output
Synchronous Primary Output
Positive Programing Supply Pin. During normal operation, it is
recommended to float this pin.
Negative Programming Supply Pin. During normal operation it is
recommended to float this pin.
BITS_CLK select input – 1.544 MHz, 0=2.048 MHz
Holdover Good Output Flag – 1=Holdover Available
JTAG TDO pin
JTAG TCK pin
Module Ground
SPI Port Clock input
SPI Port Data input
3.3 Vdc VCC Supply Input
SPI Port Enable input – Active Low
Module Reset – Active Low, 10 ms Hold time
SPI Port Data Output
SPI Port Interrupt Output – Active low
Master/Slave select input – 1=Master, 0=Slave
O
O
O
I
I
I
O
I
I
I
I
O
O
I
Data Sheet #:
TM083
© Copyright 2010 The Connor-Winfield Corp.
Page 3
of
36
Rev:
03
Date:
02/11/10
All Rights Reserved
Specifications subject to change without notice
Pin Diagram
Figure 2
LOS
LOL
M/S REF
REF1
REF2
REF3
REF4
TDI
TMS
TRST
BITS_CLK
M/S_OUT
OUTPUT1
VPP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SM3G
28
27
26
25
24
23
MASTER SELECT
SPI_INT
SPI_OUT
RESET
SPI_ENBL
Vcc
SPI_IN
SPI_CLK
GND
TCK
TDO
HOLD_GOOD
T1/E1
VPN
(TOP VIEW)
22
21
20
19
18
17
16
15
Register Map
Table 3
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0a
0x0b
0x0c
0x0d
0x0e
Reg Name
Chip_ID_Low
Chip_ID_High
Chip_Revision
Bandwidth
Ctl_Mode
Op_Mode
Max_Pullin_Range
M/S REF_Activity
Ref_Activity
Ref_Pullin_Sts
Ref_Qualified
Ref_Mask
Ref_Available
Ref_Rev_Delay
Phase_Offset
Description
Low byte of chip ID
High byte of chip ID
Chip revision number
Bandwidth Select
Manual or automatic selection of Op_Mode,BITS clock output frequency
indication, and frame/multi-frame sync pulse width mode control
Master Free Run, Locked, or Hold Over mode, or Slave mode
Maximum pull-in range in 0.1 ppm units
Cross Reference activity
Activities of 4 reference inputs
In or out of pull-in range of 4 reference inputs
Qualification status of 4 reference inputs
Availability mask for 4 reference inputs
Availability of 4 reference inputs
Reference reversion delay time, 0 - 255 minutes
Phase offset between M/S REF & M/S Output (for the Slave in M/S operation)
in 250ps resolution
Type
R
R
R
R/W
R/W
R/W
R/W
R
R
R
R
R/W
R
R/W
R/W
Data Sheet #:
TM083
Page 4
of
36
Rev:
03
Date:
02/11/10
© Copyright 2010 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Register Map Continued
0x0f
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1a
0x1b
0x1c
0x1d
0x1e
0x1f
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x30
0x31
0x32
0x33
0x36
0x37
0x38
0x39
Calibration
Fr_Pulse_Width
DPLL_Status
Intr_Event
Intr_Enable
Ref1_Frq_Offset1
Ref2_Frq_Offset2
Ref3_Frq_Offset3
Ref4_Frq_Offset4
Reserved
Reserved
Reserved
Reserved
Ref1_Frq_Priority1
Ref2_Frq_Priority2
Ref3_Frq_Priority3
Ref4_Frq_Priority4
Reserved
Reserved
Reserved
Reserved
FreeRun Priority
History_Policy
History_CMD
HoldOver_Time
Cfgdata
Cfgctr_Lo
Cfgctr_Hi
Chksum
EE_Wrt_Mode
EE_Cmd
EE_Page_Num
EE_FIFO_Port
Local oscillator digital calibration in 0.05 ppm resolution
Frame sync pulse width
Digital Phase Locked Loop status
Interrupt events
Enable individual interrupt events
Ref1 frequency offset in 0.2 ppm resolution
Ref2 frequency offset in 0.2 ppm resolution
Ref3 frequency offset in 0.2 ppm resolution
Ref4 frequency offset in 0.2 ppm resolution
R/W
R/W
R
R
R/W
R
R
R
R
Ref1 frequency and priority
Ref2 frequency and priority
Ref3 frequency and priority
Ref4 frequency and priority
R/W
R/W
R/W
R/W
Control and Priority for designation of Free Run as a reference
Sets policy for Hold Over history accumulation
Save, restore and flush comands for Hold Over history
Indicates the time since entering Hold Over state
Configuration data write register
Configuration data write counter, low byte
Configuration data write counter, high byte
Configuration data checksum pass/fail indicator
Disables/Enables writing to the external EEPROM
Read/Write command & ready indication register for ext. EEPROM access
Page number for external EEPROM access
Read/Write data for external EEPROM access
R/W
R/W
R/W
R
R/W
R
R
R
R/W
R/W
R/W
R/W
Data Sheet #:
TM083
© Copyright 2010 The Connor-Winfield Corp.
Page 5
of
36
Rev:
03
Date:
02/11/10
All Rights Reserved
Specifications subject to change without notice
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