DDR SDRAM 1Gb M-die (x4, x8) Pb-Free
DDR SDRAM
1Gb M-die DDR SDRAM Specification
66 TSOP-II with Pb-Free
(RoHS compliant)
Revision 1.1
October, 2004
Revision 1.1 October, 2004
DDR SDRAM 1Gb M-die (x4, x8) Pb-Free
1Gb M-die Revision History
Revision 1.0 (February, 2004)
- First release
Revision 1.1 (October, 2004)
- Deleted x16 option.
DDR SDRAM
Revision 1.1 October, 2004
DDR SDRAM 1Gb M-die (x4, x8) Pb-Free
Key Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe
[DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• tRFC(Refresh row cycle time) = 120ns
• Maximum burst refresh cycle : 8
• 66pin TSOP II
Pb-Free
package
• RoHS compliant
DDR SDRAM
Ordering Information
Part No.
K4H1G0438M-UC/LB3
K4H1G0438M-UC/LA2
K4H1G0438M-UC/LB0
K4H1G0838M-UC/LB3
K4H1G0838M-UC/LA2
K4H1G0838M-UC/LB0
128M x 8
256M x 4
Org.
Max Freq.
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
SSTL2
66pin TSOP II
Interface
Package
Operating Frequencies
B3(DDR333@CL=2.5)
Speed @CL2
Speed @CL2.5
*CL : CAS Latency
133MHz
166MHz
A2(DDR266@CL=2.0)
133MHz
133MHz
B0(DDR266@CL=2.5)
100MHz
133MHz
Revision 1.1 October, 2004
DDR SDRAM 1Gb M-die (x4, x8) Pb-Free
Pin Description
DDR SDRAM
128Mb x 8
256Mb x 4
V
DD
DQ
0
V
DDQ
NC
DQ
1
V
SSQ
NC
DQ
2
V
DDQ
NC
DQ
3
V
SSQ
NC
NC
V
DDQ
NC
A
13
V
DD
NC
NC
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
V
DD
NC
V
DDQ
NC
DQ
0
V
SSQ
NC
NC
V
DDQ
NC
DQ
1
V
SSQ
NC
NC
V
DDQ
NC
A
13
V
DD
NC
NC
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
V
SS
NC
V
SSQ
NC
DQ
3
V
DDQ
NC
NC
V
SSQ
NC
DQ
2
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
V
SS
DQ
7
V
SSQ
NC
DQ
6
V
DDQ
NC
DQ
5
V
SSQ
NC
DQ
4
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
66Pin TSOPII
(400mil x 875mil)
(0.65mm Pin Pitch)
Bank Address
BA0~BA1
Auto Precharge
A10
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
1Gb TSOP-II Package Pinout
Organization
256Mx4
128Mx8
Row Address
A0~A13
A0~A13
Column Address
A0-A9, A11, A12
A0-A9, A11
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Revision 1.1 October, 2004
DDR SDRAM 1Gb M-die (x4, x8) Pb-Free
Package Physical Demension
DDR SDRAM
Units : Millimeters
(0.80)
(0.50)
(10×)
(10×)
0.125
+0.075
-0.035
(0.50)
0×~8×
(R
0.2
5
)
#66
#34
10.16±0.10
(1.50)
#1
(1.50)
#33
0.665±0.05
0.210±0.05
(0.80)
0.
15
)
0.05 MIN
(0.71)
0.65TYP
0.65±0.08
0.30±0.08
(10×)
0.10 MAX
[
0.075 MAX ]
NOTE
1. (
) IS REFERENCE
2. [
] IS ASS’Y OUT QUALITY
(R
66pin TSOPII / Package dimension
Revision 1.1 October, 2004
(R
0.
25
)
(4
×
)
(R
0.1
5)
(10×)
1.20MAX
22.22±0.10
1.00±0.10
0.25TYP
0.45~0.75
11.76±0.20
(10.16)
FPGA/CPLD
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