ers. These devices have an automatic power-down feature,
reducing the power consumption by over 99% when deselect-
ed. The CY62256V family is available in the standard
450-mil-wide (300-mil body width) SOIC, TSOP, and reverse
TSOP packages.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O
0
through I/O
7
) is written into the memory location addressed by
the address present on the address pins (A
0
through A
14
).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
Functional Description
The CY62256V family is composed of three high-performance
CMOS static RAM’s organized as 32,768 words by 8 bits. Easy
memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and three-state driv-
Logic Block Diagram
Pin Configurations
SOIC
Top View
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
4
A
3
A
2
A
1
OE
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
C62256V–2
INPUTBUFFER
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
CE
WE
OE
A
14
A
13
C62256V–1
I/O
0
I/O
1
ROW DECODER
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
512x512
Y
ARRA
COLUMN
DECODER
A
12
A
11
A
1
A
0
POWER
DOWN
I/O
6
I/O
7
A
11
A
10
A
9
A
8
A
7
A
6
A
5
V
CC
WE
A
4
A
3
A
2
A
1
OE
7
6
5
4
3
2
1
28
27
26
25
24
23
22
8
9
10
11
12
13
14
15
16
17
18
19
20
21
TSOP I
Reverse Pinout
Top View
(not
to scale)
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
GND
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CE
A
0
C62256V–4
OE
A
1
A
2
A
3
A
4
WE
V
CC
A
5
A
6
A
7
A
8
A
9
A
10
A
11
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
TSOP I
Top View
(not to scale)
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
14
A
13
A
12
C62256V–3
Cypress Semiconductor Corporation
Document #: 38-05057 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised August 31, 2001
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
..................................... −65°C
to +150°C
Ambient Temperature with
Power Applied................................................... 0°C to +70°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14).................................................−0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................... −0.5V
to V
CC
+ 0.5V
DC Input Voltage
[1]
.................................... −0.5V
to V
CC
+ 0.5V
CY62256V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0
°
C to +70
°
C
−40
°
C to +85
°
C
V
CC
1.6V to 3.6V
1.6V to 3.6V
Note:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
Product Portfolio
Power Dissipation (LL Devices)
Product
Min.
CY62256V
CY62256V25
CY62256V18
2.7V
2.3V
1.6V
V
CC
Range
Typ.
3.0
2.5V
1.8V
Max.
3.6V
2.7V
2.0V
70 ns
100 ns
200 ns
Speed
Operating (I
CC
)
Typical
11 mA
9 mA
5 mA
Maximum
30 mA
15 mA
10 mA
Standby (I
SB2
)
Typical
0.1
µA
0.1
µA
0.1
µA
Maximum
5
µA
4
µA
3
µA
Electrical Characteristics
Over the Operating Range
CY62256V-70
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
V
CC
Operating Supply
Current
Automatic CE Power-Down
Current— TTL Inputs
Automatic CE
Power-Down Current—
CMOS Inputs
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
V
CC
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Com’l
Std/L
/LL
Std/L
/LL
Std/ L
LL
LL
Test Conditions
V
CC
= Min., I
OH
=
−1.0
mA
V
CC
= Min., I
OL
= 2.1 mA
2.2
−0.5
−1
−1
11
100
0.1
Min.
2.4
0.4
V
CC
+0.3V
0.8
+1
+1
30
300
50
5
10
Typ.
[2]
Max.
Unit
V
V
V
V
µA
µA
mA
µA
µA
µA
µA
Max. V
CC
, CE > V
IH
, V
IN
> V
IH
Com’l
or V
IN
< V
IL
, f = f
MAX
Max. V
CC
, CE > V
CC
– 0.3V Com’l
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V,
f=0
Ind’l
Electrical Characteristics
Over the Operating Range
CY62256V25-100
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
GND < V
I
< V
CC
Test Conditions
V
CC
= Min., I
OH
=
−0.1
mA
V
CC
= Min., I
OL
= 0.1 mA
1.7
−0.3
−1
Min.
2
0.4
Vcc +
0.3V
0.7
+1
Typ.
[2]
Max.
Unit
V
V
V
V
µA
Document #: 38-05057 Rev. **
Page 2 of 13
PRELIMINARY
Electrical Characteristics
Over the Operating Range (continued)
CY62256V
CY62256V25-100
Parameter
I
OZ
I
CC
I
SB1
Description
Output Leakage Cur-
rent
V
CC
Operating Supply
Current
Automatic CE Pow-
er-Down Current—
TTL Inputs
Automatic CE
Power-Down Current
— CMOS Inputs
Test Conditions
GND < V
O
< V
CC
, Output Disabled
V
CC
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Com’l
Stnd/L
/LL
Stnd/L
/LL
Stnd/L
LL
LL
Min.
−1
14
75
Typ.
[2]
Max.
+1
23
225
Unit
µA
mA
µA
Max. V
CC
, CE > V
IH
, V
IN
> V
IH
Com’l
or V
IN
< V
IL
, f = f
MAX
Max. V
CC
, CE > V
CC
−
0.3V Com’l
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V,
f=0
Ind’l
I
SB2
0.1
40
4
8
µA
µA
µA
Electrical Characteristics
Over the Operating Range
CY62256V18-200
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage
Current
V
CC
Operating Supply
Current
Automatic CE Pow-
er-Down Current— TTL
Inputs
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
V
CC
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Com’l
Stnd/L
/LL
Stnd/L
/LL
Stnd/L
LL
Ind’l
LL
Test Conditions
V
CC
= Min., I
OH
=
−0.1
mA
V
CC
= Min., I
OL
= 0.1 mA
0.7*Vcc
−0.5
−1
−1
10
56
Min.
0.8*Vcc
0.2
V
CC
+0.3V
0.2*Vcc
+1
+1
17
165
Typ.
[2]
Max.
Unit
V
V
V
V
µA
µA
mA
µA
Max. V
CC
, CE > V
IH
,
Com’l
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
Com’l
I
SB2
Automatic CE
Max. V
CC
, CE > V
CC
– 0.3V
Power-Down Current— V
IN
> V
CC
– 0.3V or V
IN
< 0.3V,
f=0
CMOS Inputs
0.1
30
3
6
µA
µA
µA
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 3.0V
Max.
6
8
Unit
pF
pF
Notes:
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= Vcc Typ., T
A
= 25°C, and t
AA
=70ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05057 Rev. **
Page 3 of 13
PRELIMINARY
AC Test Loads and Waveforms
R1
Vcc
OUTPUT
50 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
R2
Vcc
10%
GND
<
5 ns
C62256V–5
CY62256V
ALL INPUT PULSES
90%
90%
10%
<
5 ns
C62256V–6
THÉVENIN EQUIVALENT
R
th
V
th
OUTPUT
AC Test Load
Vcc
R1
R2
RTH
VTH
3.3 V
1103
1554
645
1.75V
2.5V
16.6K
15.4K
8K
1.2V
1.8V
13.6K
11.4K
6.2K
0.82V
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
V
CC
for Data Retention
Data Retention Current
Coml Stnd/L V
CC
= 1.6
CE > V
CC
– 0.3V,
LL
V
IN
> V
CC
– 0.3V or
Ind.
LL
V
IN
< 0.3V
0
t
RC
Conditions
[4]
Min.
1.4
30
0.1
3
6
Typ.
[2]
Max.
Unit
V
uA
uA
uA
ns
ns
t
CDR[3]
t
R[3]
Chip Deselect to Data
Retention Time
Operation Recovery Time
Data Retention Waveform
DATA RETENTION MODE
V
CC
1.8V
t
CDR
CE
C62256V–7
V
DR
> 1.4V
1.8V
t
R
Document #: 38-05057 Rev. **
Page 4 of 13
PRELIMINARY
Switching Characteristics
Over the Operating Range
[5]
CY62256V-70
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
[8,9]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[6, 7]
WE HIGH to Low Z
[6]
10
70
60
60
0
0
50
30
0
25
10
100
90
90
0
0
80
60
0
50
10
200
180
180
0
0
160
100
0
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[6]
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[6]
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
0
70
10
25
0
100
5
25
10
50
0
10
70
35
5
50
10
70
70
10
100
75
10
100
100
10
200
Description
Min.
Max.
CY62256V
CY62256V25-100 CY62256V18-200
Min.
Max.
Min.
Max.
Unit
ns
200
200
125
75
75
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
ns
ns
Switching Waveforms
Read Cycle No. 1
[10,
11]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
C62256V–8
[10, 11]
Notes:
4. No input may exceed V
CC
+0.3V.
5. Test conditions assume signal transition time of 5 ns or less timing reference levels of Vcc/2, input pulse levels of 0 to Vcc, and output loading of the specified
I
OL
/I
OH
and 100-pF load capacitance.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
1 Introduction
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