January 2007
HYS64D[16/32/64][300/301/320][G/H]U–5–C
HYS72D[32/64][300/301/320][G/H]U–5–C
HYS64D[16/32/64][300/301/320][G/H]U–6–C
HYS72D[32/64][300/301/320][G/H]U–6–C
184- Pin Unbuffered DDR SDRAM Modules
UDIMM
DDR SDRAM
Internet Data Sheet
Rev. 1.11
Internet Data Sheet
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
HYS64D[16/32/64][300/301/320][G/H]U–5–C, HYS72D[32/64][300/301/320][G/H]U–5–C,
HYS64D[16/32/64][300/301/320][G/H]U–6–C, HYS72D[32/64][300/301/320][G/H]U–6–C
Revision History: 2007-01, Rev. 1.11
Page
All
All
Subjects (major changes since last revision)
Qimonda update
Adapted internet edition
Previous Revision: Rev. 1.1
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
09152006-1LHY-N6G4
2
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Overview
1
1.1
•
•
•
•
•
•
•
•
•
•
•
•
Overview
Features
184-Pin Unbuffered Double Data Rate SDRAM (ECC and non-parity) for PC and Server main memory
applications
One rank 16M x 64, 32M
×
64, 32M
×
72 and two ranks 64M
×
64, 64M
×
72 organization
JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (±0.2V) power supply
and +2.6V (±0.1V) ppower supply for DDR400
Built with 256 Mbit DDR SDRAM in P-TSOPII-66-1 package
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Serial Presence Detect with E
2
PROM
JEDEC standard MO-206 form factor: 133.35 mm
×
31.75 mm
×
4.00 mm max.
Jedec standard reference layout
Gold plated contacts
DDR400 Speed Grade supported
Performance
–5
DDR400B
PC3200–3033
@ CL = 3
@ CL = 2.5
@ CL = 2
–6
DDR333B
PC2700–2533
166
166
133
Unit
—
—
MHz
MHz
MHz
Table 1
Product Type Speed Code
Module Speed Grade
Component Module
Max. Clock Frequency
f
CK3
f
CK2.5
f
CK2
200
166
133
1.2
Description
The HYS64D[16/32/64][300/301/320][G/H]U–5–C, HYS72D[32/64][300/301/320][G/H]U–5–C,
HYS64D[16/32/64][300/301/320][G/H]U–6–C and HYS72D[32/64][300/301/320][G/H]U–6–C are industry
standard 184-Pin Unbuffered Double Data Rate SDRAM (UDIMM) organized as 16M
×64,
32M
×64
and 64M
×64
for non-parity and 32M
×
72 and 64M
×
72 for ECC main memory applications. The memory array is designed
with 256Mbit Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the
printed circuit board. The DIMMs feature serial presence detect (SPD) based on a serial E
2
PROM device using
the 2-pin I
2
C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are
available to the customer
Internet Data Sheet
3
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Overview
Table 2
Ordering Information for Lead-Free Products
Compliance Code
PC3200U–30330–C0
PC3200U–30330–A0
PC3200U–30330–A0
PC3200U–30330–B0
PC3200U–30330–B0
PC2700U–25330–C0
PC2700U–25330–A0
PC2700U–25330–A0
PC2700U–25330–B0
PC2700U–25330–B0
Description
one rank 128MB DIMM
one rank 256MB DIMM
one rank 256MB ECC-DIMM
two ranks 512MB DIMM
SDRAM Technology
256 Mbit (×16)
256 Mbit (×8)
256 Mbit (×8)
256 Mbit (×8)
Product Type
2)
PC3200 (CL=3)
HYS64D16301GU–5–C
HYS64D32300GU–5–C
HYS72D32300GU–5–C
HYS64D64320GU–5–C
HYS72D64320GU–5–C
PC2700 (CL=2.5)
HYS64D16301GU–6–C
HYS64D32300GU–6–C
HYS72D32300GU–6–C
HYS64D64320GU–6–C
HYS72D64320GU–6–C
two ranks 512MB ECC-DIMM 256 Mbit (×8)
one rank 128MB DIMM
one rank 256MB DIMM
one rank 256MB ECC-DIMM
two ranks 512MB DIMM
256 Mbit (×16)
256 Mbit (×8)
256 Mbit (×8)
256 Mbit (×8)
two ranks 512MB ECC-DIMM 256 Mbit (×8)
Table 3
Ordering Information for Lead-Free (RoHS
1)
Compliant Products)
Compliance Code
PC3200U–30330–C0
PC3200U–30330–A0
PC3200U–30330–A0
PC3200U–30330–B0
PC3200U–30330–B0
PC2700U–25330–C0
PC2700U–25330–A0
PC2700U–25330–A0
PC2700U–25330–B0
PC2700U–25330–B0
Description
one rank 128MB DIMM
one rank 256MB DIMM
one rank 256MB ECC-DIMM
two ranks 512MB DIMM
two ranks 512MB ECC-DIMM
one rank 128MB DIMM
one rank 256MB DIMM
one rank 256MB ECC-DIMM
two ranks 512MB DIMM
two ranks 512MB ECC-DIMM
SDRAM Technology
256 Mbit (×16)
256 Mbit (×8)
256 Mbit (×8)
256 Mbit (×8)
256 Mbit (×8)
256 Mbit (×16)
256 Mbit (×8)
256 Mbit (×8)
256 Mbit (×8)
256 Mbit (×8)
Product Type
2)
PC3200 (CL=3)
HYS64D16301HU–5–C
HYS64D32300HU–5–C
HYS72D32300HU–5–C
HYS64D64320HU–5–C
HYS72D64320HU–5–C
PC2700 (CL=2.5)
HYS64D16301HU–6–C
HYS64D32300HU–6–C
HYS72D32300HU–6–C
HYS64D64320HU–6–C
HYS72D64320HU–6–C
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic
equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January
2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and
polybrominated biphenyl ethers.
2) All part numbers end with a place code designating the silicon-die revision. Reference information available on request.
Example: HYS72D32000HU-6-C, indicating rev. C dies are used for SDRAM components. The Compliance Code is printed
on the module labels describing the speed sort (for example “PC2700”), the latencies and SPD code definition (for example
“20330” means CAS latency of 2.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks, Row Precharge latency of
3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module.
Internet Data Sheet
4
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
Unbuffered DDR SDRAM Modules
Pin Configuration
2
Pin Configuration
Table 4
Pin# Name
122
27
141
118
115
I
NC
I
I
I
NC
I
I
I
I
NC
I
I
NC
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
—
SSTL
SSTL
SSTL
—
SSTL
SSTL
SSTL
SSTL
—
SSTL
SSTL
—
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Clock Enable Rank 0
Clock Enable Rank 1
Note: 2-rank module
NC
Note: 1-rank module
Chip Select Rank 0
Chip Select Rank 1
Note: 2-rank module
NC
Note: 1-rank module
Row Address Strobe
Column Address
Strobe
Write Enable
Bank Address Bus
2:0
Address Bus 11:0
Data Signals
2
4
6
8
94
95
98
99
12
13
19
20
105
106
109
110
23
24
28
31
114
117
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Rev. 1.11, 2007 - 01
09152006-1LHY-N6G4
Data Bus 63:0
NC
NC
—
Complement Clock
Signals 2:0
167
NC
A13
NC
I
—
SSTL
Clock Signals 2:0
A8
A9
A10
AP
A11
A12
Pin Configuration of UDIMM
(cont’d)
Pin Buffer Function
Type Type
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Address Signal 12
Note: Module based on
256 Mbit or larger
dies
Note: 128 Mbit based
module
Address Signal 13
Note: 1 Gbit based
module
Note: Module based on
512 Mbit or
smaller dies
Address Bus 11:0
The pin configuration of the Unbuffered DDR SDRAM
DIMM is listed by function in
Table 4
(184 pins). The
abbreviations used in columns Pin and Buffer Type are
explained in
Table 5
and
Table 6
respectively. The pin
numbering is depicted in
Figure 1.
Table 4
Pin# Name
Clock Signals
137
16
76
138
17
75
21
111
CK0
NC
CK1
CK2
CK0
NC
CK1
CK2
CKE0
CKE1
Pin Configuration of UDIMM
Pin Buffer Function
Type Type
Control Signals
157
158
S0
S1
154
65
63
59
52
48
43
41
130
37
32
125
29
RAS
CAS
WE
BA0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
Address Signals
Internet Data Sheet
5
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