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IDT74ALVCH16334PA

产品描述Bus Driver, ALVC/VCX/A Series, 1-Func, 16-Bit, True Output, CMOS, PDSO48, 0.50 MM PITCH, TSSOP-48
产品类别逻辑    逻辑   
文件大小104KB,共7页
制造商IDT (Integrated Device Technology)
下载文档 详细参数 全文预览

IDT74ALVCH16334PA概述

Bus Driver, ALVC/VCX/A Series, 1-Func, 16-Bit, True Output, CMOS, PDSO48, 0.50 MM PITCH, TSSOP-48

IDT74ALVCH16334PA规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称IDT (Integrated Device Technology)
零件包装代码TSSOP
包装说明TSSOP, TSSOP48,.3,20
针数48
Reach Compliance Codenot_compliant
控制类型ENABLE LOW
系列ALVC/VCX/A
JESD-30 代码R-PDSO-G48
JESD-609代码e0
长度12.5 mm
逻辑集成电路类型BUS DRIVER
最大I(ol)0.024 A
湿度敏感等级1
位数16
功能数量1
端口数量2
端子数量48
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装等效代码TSSOP48,.3,20
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源3.3 V
Prop。Delay @ Nom-Sup3.3 ns
传播延迟(tpd)4.5 ns
认证状态Not Qualified
座面最大高度1.2 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)2.7 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Tin/Lead (Sn85Pb15)
端子形式GULL WING
端子节距0.5 mm
端子位置DUAL
宽度6.1 mm

IDT74ALVCH16334PA文档预览

IDT74ALVCH16334
3.3V CMOS 16-BIT UNIVERSAL BUS DRIVER W/3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT
UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
AND BUS-HOLD
FEATURES:
0.5 MICRON CMOS Technology
Typical t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.635mm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
– Extended commercial range of – 40°C to + 85°C
– V
CC
= 3.3V ± 0.3V, Normal Range
– V
CC
= 2.7V to 3.6V, Extended Range
– V
CC
= 2.5V ± 0.2V
– CMOS power levels (0.4µ W typ. static)
– Rail-to-Rail output swing for increased noise margin
Drive Features for ALVCH16334:
– High Output Drivers: ±24mA
– Suitable for heavy loads
IDT74ALVCH16334
DESCRIPTION:
This 16-bit universal bus driver is built using advanced dual metal
CMOS technology. Data flow from A to Y is controlled by the output-
enable (OE) input. The device operates in the transparent mode when
the latch-enable (LE) input is low. When LE is high, the A data is latched
if the clock (CLK) input is held at a high or low logic level. If LE is high, the
A data is stored in the latch/flip-flop on the low-to-high transition of CLK.
When OE is high, the outputs are in the high-impedance state.
The ALVCH16334 has been designed with a ±24mA output driver.
This driver is capable of driving a moderate to heavy load while
maintaining speed performance.
The ALVCH16334 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
APPLICATIONS:
SDRAM Modules
PC Motherboards
Workstations
Functional Block Diagram
OE
1
CLK
LE
48
25
A
1
47
1
D
2
Y
1
C
1
CLK
TO 15 OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
APRIL 1999
DSC-4493/1
IDT74ALVCH16334
3.3V CMOS 16-BIT UNIVERSAL BUS DRIVER W/3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE
Y
1
Y
2
GND
Y
3
Y
4
V
CC
Y
5
Y
6
GND
Y
7
Y
8
Y
9
Y
10
GND
Y
11
Y
12
V
CC
Y
13
Y
14
GND
Y
15
Y
16
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SO 48-1
SO 48-2
SO 48-3
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CLK
A
1
A
2
GND
A
3
A
4
V
CC
A
5
A
6
GND
A
7
A
8
A
9
A
10
GND
A
11
A
12
V
CC
A
13
A
14
GND
A
15
A
16
LE
ABSOLUTE MAXIMUM RATING
Symbol
V
TERM(2)
V
TERM(3)
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage
with Respect to GND
Terminal Voltage
with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
>
V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through
each V
CC
or GND
(1)
Unit
V
V
°C
mA
mA
mA
mA
NEW16link
Max.
– 0.5 to + 4.6
– 0.5 to
V
CC
+ 0.5
– 65 to + 150
– 50 to + 50
± 50
– 50
±100
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
CAPACITANCE
(T
A
= +25
o
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
NEW16link
NOTE:
1. As applicable to the device type.
FUNCTION TABLE
Inputs
OE
H
L
L
LE
X
L
L
H
H
H
(1)
Output
SSOP/TSSOP/TVSOP
TOP VIEW
CLK
X
X
X
L or H
Ax
X
L
H
L
H
X
Yx
Z
L
H
L
H
Y
0(2)
PIN DESCRIPTION
Pin Names
OE
CLK
LE
Ax
Yx
Description
3-State Output Enable Inputs (Active LOW)
Register Input Clock
Latch Enable (Transparent LOW)
Data Inputs
(1)
L
L
L
3-State Outputs
NOTE:
1. These pins have “Bus-Hold.” All other pins are standard inputs,
outputs, or I/Os.
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑ =
LOW-to-HIGH Transition
2. Output level before the indicated steady-state input conditions were es
tablished.
2
IDT74ALVCH16334
3.3V CMOS 16-BIT UNIVERSAL BUS DRIVER W/3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
Quiescent Power Supply
Current Variation
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
0.6V,
other inputs at V
CC
or GND
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Min.
1.7
2
Typ.
(1)
– 0.7
100
0.1
Max.
0.7
0.8
±5
±5
± 10
± 10
– 1.2
40
µA
µA
V
mV
µA
µA
V
Unit
V
750
µA
NEW16link
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
NEW16link
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3.0V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2.0V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
– 45
45
Typ.
(2)
Max.
± 500
Unit
µA
µA
µA
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3
IDT74ALVCH16334
3.3V CMOS 16-BIT UNIVERSAL BUS DRIVER W/3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
V
CC
= 2.7V
V
CC
= 3.0V
I
OL
= 12mA
I
OL
= 24mA
2
Max.
0.2
0.4
0.7
0.4
0.55
NEW16link
Unit
V
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to + 85°C.
OPERATING CHARACTERISTICS, T
A
= 25
o
C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance
Outputs enabled
Power Dissipation Capacitance
Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
32
7
V
CC
= 3.3V ± 0.3V
Typical
37
11
Unit
pF
pF
4
IDT74ALVCH16334
3.3V CMOS 16-BIT UNIVERSAL BUS DRIVER W/3-STATE OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
W
t
W
t
SU
t
SU
t
SU
t
H
t
H
t
SK
(o)
Parameter
Propagation Delay
Ax to Yx
Propagation Delay
LE to Yx
Propagation Delay
CLK to Yx
Output Enable Time
OE to Yx
Output Disable Time
OE to Yx
Pulse Duration, LE LOW
Pulse Duration, CLK HIGH or LOW
Setup Time, data before CLK↑
Setup Time, data before LE↑, CLK HIGH
Setup Time, data before LE↑, CLK LOW
Hold Time, data after CLK↑
Hold Time, data after LE↑,
CLK HIGH or LOW
Output Skew
(2)
(1)
V
CC
= 2.5V ± 0.2V
Min
.
150
1
1
1
1
1
3.3
3.3
1.4
1.2
1.4
0.9
1.2
Max.
3.7
4.8
4.4
5.4
4.1
V
CC
= 2.7V
Min
.
150
3.3
3.3
1.7
1.6
1.5
0.8
1.1
Max.
3.6
5
4.5
5.4
4.5
V
CC
= 3.3V ± 0.3V
Min
.
150
1.1
1.3
1
1.1
1.7
3.3
3.3
1.5
1.3
1.2
0.9
1.1
Max.
3.3
4.4
4.1
4.6
4.4
500
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
NOTES:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
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