IDTQS74FCT2823AT/BT
HIGH-SPEED CMOS BUS INTERFACE 9-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
HIGH-SPEED CMOS
BUS INTERFACE
9-BIT REGISTER
FEATURES:
•
•
•
•
•
•
IDTQS74FCT2823AT/BT
DESCRIPTION:
CMOS power levels: <7.5mW static
Undershoot clamp diodes on all outputs
True TTL input and output compatibility
Ground bounce controlled outputs
Reduced output swing of 0 to 3.5V
Ω
Built-in 25Ω series resistor outputs reduce reflection and other
system noise
• A and B speed grades
• I
OL
= 12mA
• Available in QSOP package
The IDTQS74FCT2823T is a 9-bit high-speed CMOS TTL-compatible
buffered register with 3-state outputs, with a 25Ω resister that is useful for
driving transmission lines and reducing system noise. The 2823 series parts
can replace the 823 series to reduce noise in an existing design. All inputs
have clamp diodes for undershoot noise suppression. All outputs have
ground bounce suppression. Outputs will not load an active bus when Vcc
is removed from the device.
FUNCTIONAL BLOCK DIAGRAM
EN
14
D
Dx
CP
13
Q
25Ω
CP
CLR
Yx
CLR
OE
11
1
INDUSTRIAL TEMPERATURE RANGE
1
c
2004 Integrated Device Technology, Inc.
JANUARY 2004
DSC-5257/5
IDTQS74FCT2823AT/BT
HIGH-SPEED CMOS BUS INTERFACE 9-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
CLR
GND
1
2
3
4
5
6
7
8
9
10
11
12
QSOP
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current Max Sink Current/Pin
Input Diode Current, V
IN
< 0
Output Diode Current, V
OUT
< 0
Max
–0.5 to +7
–65 to +150
120
–20
–50
Unit
V
°C
mA
mA
mA
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
EN
CP
V
TERM
T
STG
I
OUT
I
IK
I
OK
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
(2)
Parameter
(1)
Input Capacitance
Input Capacitance
Output Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
IN
= 0V
V
OUT
= 0V
V
OUT
= 0V
Typ.
4
8
6
8
Max.
—
—
—
—
Unit
pF
pF
pF
pF
C
IN
(3)
C
OUT
(4)
C
OUT
(5)
NOTES:
1. This parameter is measured at characterization but not tested.
2. Pins 1, 3-11, 13.
3. Pin 2.
4. Pins 15-22.
5. Pins 14, 23.
PIN DESCRIPTION
LOGIC SYMBOL
Pin Names
Dx
CLR
9
9
I/O
I
I
Description
D Flip-Flop Data Inputs
When the clear input is LOW and
OE
is LOW, the Yx
outputs are LOW. When clear input is HIGH, data can
be entered into the register.
Clock Pulse for the register. Enters data into the register
on the LOW-to-HIGH transition.
Register 3-State Outputs
Clock Enable. When the clock enable is LOW, data
on the D
x
input is transferred to the Yx output on the
LOW-to-HIGH clock transition. When the clock
enable is HIGH, the Yx outputs do not change state,
regardless of the data or clock input transitions.
Output Control. When the
OE
input is HIGH, the Yx
outputs are in the high impedance state. When the
OE
input is LOW, the TRUE register data is present at the
Yx outputs.
Dx
D
CP
EN
Q
CLR
Yx
CP
Yx
EN
I
O
I
CP
EN
CLR
OE
OE
I
2
IDTQS74FCT2823AT/BT
HIGH-SPEED CMOS BUS INTERFACE 9-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
FUNCTION TABLE
(1)
Inputs
OE
H
H
H
L
H
L
H
H
L
L
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
NC = No Change
↑
= LOW-to-HIGH transition
Z = High-Impedance
Internal
Dx
L
H
X
X
X
X
L
H
L
H
CP
↑
↑
X
X
X
X
↑
↑
↑
↑
Qx
L
H
L
L
NC
NC
L
H
L
H
Outputs
Yx
Z
Z
Z
L
Z
NC
Z
Z
L
H
Function
High Z
High Z
Clear
Clear
Hold
Hold
Load
Load
Load
Load
CLR
X
X
L
L
H
H
H
H
H
H
EN
L
L
X
X
H
H
L
L
L
L
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 5.0V ±5%
Symbol
V
IH
V
IL
∆V
T
I
IH
I
IL
I
OZ
I
OR
V
IC
V
OH
V
OL
R
OUT
(3)
Parameter
Input HIGH Level
Input LOW Level
Input Hysteresis
Input HIGH Current
Input LOW Current
Off-State Output Current (Hi-Z)
Current Drive
Input Clamp Voltage
Output HIGH Voltage
Output LOW Voltage
Output Resistance
V
CC
= Max
0
≤
V
IN
≤
V
CC
—
50
—
2.4
—
18
—
—
–0.7
—
—
25
±5
—
–1.2
—
0.5
40
µA
mA
V
V
V
Ω
V
CC
= Max., V
OUT
= 2.0V
(2)
V
CC
= Min, I
IN
= -18mA , T
A
= 25°C
(2)
V
CC
= Min.
V
CC
= Min.
V
CC
= Min.
I
OH
= -15mA
I
OL
= 12mA
I
OH
= 12mA
Test Conditions
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
TLH
- V
THL
for all inputs
V
CC
= Max.
0
≤
V
IN
≤
V
CC
Min.
2
—
—
—
Typ.
(1)
—
—
0.2
—
Max.
—
0.8
—
±5
Unit
V
V
V
µA
NOTES:
1. Typical values are at V
CC
= 5.0V, T
A
= 25°C.
2. This parameter is measured at characterization but not tested.
3. R
OUT
changed on March 8, 2002. See rear page for more information.
3
IDTQS74FCT2823AT/BT
HIGH-SPEED CMOS BUS INTERFACE 9-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40°C to +85°C, V
CC
= 5.0V ± 5%
Symbol
I
CC
Parameter
Quiescent Power Supply Current
∆I
CC
Supply Current per Input TTL Inputs HIGH
I
CCD
Supply Current per Input per MHz
Test Conditions
(1)
V
CC
= Max.
freq = 0
0V
≤
V
IN
≤
0.2V or
V
CC
- 0.2V
≤
V
IN
≤
Vcc
V
CC
= Max.
V
IN
= 3.4V
(2)
freq = 0
V
CC
= Max.
Outputs Open and Enabled
One Bit Toggling
50% Duty Cycle
Other inputs at GND or Vcc
(3,4)
Min.
—
Max.
1.5
Unit
mA
—
2
mA
—
0.25
mA/MHz
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. Per TLL driven input (V
IN
= 3.4V).
3. For flip-flops, I
CCD
is measured by switching one of the data input pins so that the output changes every clock cycle. This is a measurement of device power consumption
only and does not include power to drive load capacitance or tester capacitance.
4. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
4
IDTQS74FCT2823AT/BT
HIGH-SPEED CMOS BUS INTERFACE 9-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(1)
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
SU
t
H
t
ENS
t
ENH
Parameter
Clock to Y Delay
OE
= LOW
Clock to Y Delay
OE
= LOW
(2)
Data to CP Setup Time
Data to CP Hold Time
EN
to CP Setup Time
EN
to CP Hold Time
FCT2823AT
Min.
Max.
—
10
—
4
2
4
2
20
—
—
—
—
FCT2823BT
Min.
Max.
—
7.5
—
3
1.5
3
0
15
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
NOTES:
1. C
LOAD
= 50pF, R
LOAD
= 500Ω unless otherwise noted.
2. C
LOAD
= 300pF.
TIMING REQUIREMENTS OVER OPERATING RANGE
(1)
Symbol
t
CLR
t
REC
t
PLH
t
PHL
t
PZH
t
PZL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PHZ
t
PLZ
Parameter
CLR
to Y Delay
CLR
to CP Setup Time
Clock Pulse Width
HIGH or LOW
Output Enable Time
OE
to Yx
Output Enable Time
(3)
OE
to Yx
Output Disable Time
(4)
OE
to Yx
Output Disable Time
OE
to Yx
(2)
FCT2823AT
Min.
Max.
—
11
6
—
7
—
—
—
—
—
12
23
7
9
FCT2823BT
Min.
Max.
—
9
6
—
6
—
—
—
—
—
8
—
6.5
7.5
Unit
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. C
LOAD
= 50pF, R
LOAD
= 500Ω unless otherwise noted.
2. See Test Circuits and Waveforms
3. C
LOAD
= 300pF.
4. C
LOAD
= 5pF.
5
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