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GTLP1B153 1-Bit LVTTL/GTLP Driver/Receiver Pair
June 2001
Revised February 2002
GTLP1B153
1-Bit LVTTL/GTLP Driver/Receiver Pair
General Description
The GTLP1B153 is a 1-bit bus buffer pair with separate bit
paths, that provide LVTTL-to-GTLP and GTLP-to-LVTTL
signal level translation. High speed backplane operation is
a direct result of GTLP’s reduced output swing (
<
1V),
reduced input threshold levels and output edge rate con-
trol. The edge rate control minimizes bus settling time.
GTLP is a Fairchild Semiconductor derivative of the Gun-
ning Transistor logic (GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is pro-
cess, voltage and temperature compensated. GTLP’s I/O
structure is similar to GTL and BTL but offers different out-
put levels and receiver threshold. Typical GTLP output volt-
age levels are: V
OL
=
0.5V, V
OH
=
1.5V, and V
REF
=
1V.
Features
s
Interface between LVTTL and GTLP logic levels
s
Designed with edge rate control circuitry to reduce
output noise in the GTLP port
s
V
REF
pin provides external supply reference voltage for
receiver threshold adjustability
s
Special PVT compensation circuitry to provide
consistent performance over variations of process,
supply voltage and temperature
s
TTL compatible driver and control inputs
s
Designed using Fairchild advanced BiCMOS technology
s
Bushold data inputs on A Port to eliminate the need for
external pull-up resistors for unused inputs
s
Power up/down and power off high impedance for live
insertion
s
Open drain on GTLP to support wired-or connection
s
Flow through pinout optimizes PCB layout
s
A Port source/sink
−
24mA/
+
24mA
s
B Port sink
+
50mA
Ordering Code:
Order Number
GTLP1B153M
GTLP1B153MX
GTLP1B153K8X
Package Number
M08A
M08A
MAB08A
(Preliminary)
Package Description
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TUBE]
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TAPE and REEL]
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
[TAPE and REEL]
Pin Descriptions
Pin Names
OEA
Description
LVTTL Bit Level Output Enable
(Active LOW for Receive)
Connection Diagrams
US8
V
CC
, GND, V
REF
Device Supplies
B
O
, B
I
A
O
/ A
I
B Port GTLP Outputs/ Inputs
A Port LVTTL Outputs/ Inputs
SOIC
© 2002 Fairchild Semiconductor Corporation
DS500485
www.fairchildsemi.com
GTLP1B153
Functional Description
The GTLP1B153 is a 2-bit transceiver that supports GTLP and LVTTL signal levels. Data polarity is non-inverting and the
data flow in the B-to-A direction is controlled by the OEA pin.
Functional Table
Inputs
OEA
L
L
H
OEA
X
X
B
I
L
H
X
A
I
L
H
Outputs
A
O
L
H
Z
B
O
L
B Output Data Bit Enabled
H
B Output Data Bit Enabled
(Note 1)
Description
A Output Data Bit Enabled
A Output Data Bit Enabled
A Output Data Bit High Impedance
Note 1:
Denotes that the bit would be in high impedance mode if there was no pull-up circuit due to open drain nature of the GTLP output.
Logic Diagram
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2
GTLP1B153
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
DC Output Voltage (V
O
)
Outputs 3-STATE
Outputs Active (Note 3)
DC Output Sink Current into
A Port I
OL
DC Output Source Current from
A Port I
OH
DC Output Sink Current into
B Port in the LOW State, I
OL
DC Input Diode Current (I
IK
)
V
I
<
0V
DC Output Diode Current (I
OK
)
V
O
<
0V
ESD Rating
Storage Temperature (T
STG
)
100 mA
48 mA
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
Recommended Operating
Conditions
Supply Voltage V
CC
Bus Termination Voltage (V
TT
)
GTLP
V
REF
Input Voltage (V
I
)
on A Port and Control Pins
HIGH Level Output Current (I
OH
)
A Port
LOW Level Output Current (I
OL
)
A Port
B Port
Operating Temperature (T
A
)
0.0V to V
CC
1.47V to 1.53V
0.98V to 1.02V
3.15V to 3.45V
−
48 mA
−
24 mA
+
24 mA
+
50 mA
−
40
°
C to
+
85
°
C
−
50 mA
−
50 mA
>
2000V
−
65
°
C to
+
150
°
C
Note 2:
Absolute Maximum Ratings are those values beyond which the
safety of the device cannot be guaranteed. The device should not be oper-
ated at these limits. The parametric values defined in the “Electrical Char-
acteristics” table are not guaranteed at the absolute maximum rating. The
“Recommended Operating Conditions” table will define the conditions for
actual device operation.
Note 3:
I
O
Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, V
REF
=
1.0V (unless otherwise noted).
Symbol
V
IH
V
IL
V
REF
V
TT
V
IK
V
OH
A Port
B Port
Others
B Port
Others
B Port
B Port
V
CC
=
3.15V
V
CC
=
Min to Max (Note 5)
V
CC
=
3.15V
V
OL
A Port
V
CC
=
Min to Max (Note 5)
V
CC
=
3.15V
V
CC
=
3.15V
B Port
I
I
Control Pins
A Port
B Port
I
OFF
A Port,
Control Pins
B Port
I
I (HOLD)
I
OZH
A Port
A Port
B Port
V
CC
=
0
V
CC
=
3.15V
V
CC
=
3.45V
V
I
or V
O
=
0 to 3.45V
V
I
=
0.8V
V
I
=
2.0V
V
O
=
3.45V
V
O
=
3.45V
75
−75
10
5
30
µA
V
CC
=
3.15V
V
CC
=
3.45V
V
CC
=
3.45V
V
CC
=
3.45V
V
CC
=
0
I
I
= −18
mA
I
OH
= −100 µA
I
OH
= −8
mA
I
OH
= -24 mA
I
OL
=
100
µA
I
OL
=
8 mA
I
OL
=
24 mA
I
OL
=
40 mA
I
OL
=
50 mA
V
I
=
3.45V
V
I
=
0V
V
I
=
3.45V
V
I
=
0V
V
I
=
3.45V
V
I
=
0
V
I
or V
O
=
0 to 3.45V
V
CC
- 0.2
2.4
2.2
0.2
0.4
0.5
0.4
0.55
5
−5
10
−10
5
−5
30
V
µA
µA
µA
µA
V
V
0.7V
V
REF
+
50 mV
1.0
1.5
Test Conditions
Min
V
REF
+
0.05
2.0
0.0
V
REF
−
0.05
0.8
1.3V
V
CC
−1.2
Typ
(Note 4)
V
TT
Max
Units
V
V
V
V
V
µA
µA
3
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GTLP1B153
DC Electrical Characteristics
Symbol
I
OZL
I
PU/PD
I
CC
A Port
B Port
All Ports
A Port
or B Port
∆I
CC
(Note 6)
C
i
C
O
A Port and
Control Pins
Control Pins
A and B Port
A Port
B Port
Note 4:
All typical values are at V
CC
=
3.3V and T
A
=
25°C.
(Continued)
Min
Typ
(Note 4)
−10
−5
30
11
11
11
2
3
5
5
mA
pF
pF
pF
mA
Max
Test Conditions
V
CC
=
3.45V
V
CC
=
0 to 1.5V
V
CC
=
3.45V
I
O
=
0
V
I
=
V
CC
/V
TT
or GND
V
CC
=
3.45V,
V
O
=
0V
V
O
=
0V
V
I
=
0 to 3.45V
Outputs HIGH
Outputs LOW
Outputs Disabled
One Input at V
CC
V
I
=
V
CC
,
V
TT
or 0
V
I
=
V
CC
or 0
V
I
=
V
TT
or 0
Units
µA
µA
A or Control Inputs at V
CC
or GND
−0.6V
Note 5:
For conditions shown as Min, use the appropriate value specified under recommended operating conditions.
Note 6:
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
Note:
GTLP V
REF
and V
TT
are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy. In
addition, V
TT
and R
TERM
can be adjusted beyond the recommended operating to accommodate backplane impedances other than 50Ω, but must remain
within the boundaries of the DC Absolute Maximum Ratings. Similarly, V
REF
can be adjusted to optimize noise margin.
AC Electrical Characteristics
Over recommended range of supply voltage and operating free-air temperature, V
REF
=
1.0V (unless otherwise noted).
C
L
=
30 pF for B Port and C
L
=
50 pF for A Port.
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
RISE
t
FALL
t
RISE
t
FALL
t
PZH
, t
PZL
t
PHZ
, t
PLZ
From
(Input)
A
B
To
(Output)
B
A
1.2
0.8
1.4
1.6
Min
Typ
(Note 7)
2.9
2.0
2.5
2.7
1.5
1.8
2.5
2.2
1.2
1.4
2.7
2.8
5.3
4.9
7.3
4.5
4.4
5.0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
Transition Time, B Outputs (20% to 80%)
Transition Time, B Outputs (80% to 20%)
Transition Time, C Outputs (10% to 90%)
Transition Time, C Outputs (90% to 10%)
OEA
A
Note 7:
All typical values are at V
CC
=
3.3V, and T
A
=
25°C.
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4
传感器
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