Integrated
Circuit
Systems, Inc.
ICS9112-17
Low Skew Output Buffer
General Description
The
ICS9112-17
is a high performance, low skew, low jitter
zero delay buffer. It uses a phase lock loop (PLL)
technology to align, in both phase and frequency, the REF
input with the CLKOUT signal. It is designed to distribute
high speed clocks in PC systems operating at speeds
from 25 to 133 MHz.
ICS9112-17
is a zero delay buffer that provides
synchronization between the input and output. The
synchronization is established via CLKOUT feed back to
the input of the PLL. Since the skew between the input and
output is less than +/- 350 pS, the part acts as a zero delay
buffer.
The
ICS9112-17
has two banks of four outputs controlled
by two address lines. Depending on the selected address
line, bank B or both banks can be put in a tri-state mode.
In this mode, the PLL is still running and only the output
buffers are put in a high impedance mode. The test mode
shuts off the PLL and connects the input directly to the
output buffers (see table below for functionality).
The
ICS9112-17
comes in a sixteen pin 150 mil SOIC or
16 pin SSOP package. In the absence of REF input, will
be in the power down mode. In this mode, the PLL is turned
off and the output buffers are pulled low. Power down mode
provides the lowest power consumption for a standby
condition.
Features
•
•
•
•
•
•
•
Zero input - output delay
Frequency range 25 - 133 MHz (3.3V)
High loop filter bandwidth ideal for Spread Spectrum
applications.
Less than 200 ps cycle to cycle Jitter
Skew controlled outputs
Skew less than 250 ps between outputs
Available in 16 pin, 150 mil SSOP & SOIC package
Pin Configuration
Block Diagram
16 pin SSOP & SOIC
Functionality
FS2 FS1
0
0
1
1
0
1
0
1
CLKA
(1, 4)
Driven
CLKB
(1, 4)
Tristate
CLKOUT
Driven
Driven
PLL
Bypass
Mode
Driven
Output
Source
PLL
PLL
REF
PLL
PLL
Shutdown
N
N
Y
N
Tristate Tristate
P LL
PLL
Bypass Bypass
Mode
Mode
Driven
Driven
0051L—08/03/07
ICS9112-17
Pin Descriptions
PIN NUMBER
1
2
3
4, 13
5, 12
6
7
8
9
10
11
14
15
16
PIN NAME
REF
2
CLKA1
3
CLKA2
3
VDD
GND
CLKB1
3
CLKB2
3
FS2
4
FS1
4
CLKB3
3
CLKB4
3
CLKA3
3
CLKA4
3
CLKOUT
3
TYPE
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
DESCRIPTION
Input reference frequency.
Buffered clock output, Bank A
Buffered clock output, Bank A
Power Supply (3.3V)
Ground
Buffered clock output. Bank B
Buffered clock output. Bank B
Select input, bit 2
Select input, bit 1
Buffered clock output. Bank B
Buffered clock output. Bank B
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered clock output, internal feedback on this pin
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. Weak pull-down
3. Weak pull-down on all outputs
4. Weak pull-ups on these inputs
0051L—08/03/07
2
ICS9112-17
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input & Supply
T
A
= 0 - 70C; Supply Voltage V
DD
= 5.0 V +/-10% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Operating current
Input frequency
Input Capacitance
1
SYMBOL
CONDITIONS
V
IH
V
IL
V
IN
= V
DD
I
IH
V
IN
= 0 V;
I
IL
C
L
= 0 pF; F
IN
@ 66M
I
DD1
F
i1
C
IN1
V
DD
= 3.3 V; All Outputs Loaded
Logic Inputs
MIN
2.0
GND -0.5
TYP
MAX UNITS
2.5 VDD +0.5
V
0.8
V
0.1
100
uA
19
50
uA
45
65
mA
133
5
MHz
pF
25
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input & Supply
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-10% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Operating current
Input frequency
Input Capacitance
1
SYMBOL
CONDITIONS
V
IH
V
IL
V
IN
= V
DD
I
IH
I
IL
V
IN
= 0 V;
C
L
= 0 pF; F
IN
@ 66M
I
DD1
F
i 1
C
IN1
V
DD
= 3.3 V; All Outputs Loaded
Logic Inputs
MIN
2.0
GND-0.3
TYP
2.0
0.1
19
30
MAX UNITS
V
DD
+0.3 V
0.8
V
100
uA
50
uA
45
mA
133
5.0
MHz
pF
25
Guarenteed by design, not 100% tested in production.
0051L—08/03/07
3
ICS9112-17
Electrical Characteristics - OUTPUT
T
A
= 0 - 70°C; V
DD
= V
DDL
= 5.0 V +/-10%; C
L
= 20 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
Output Impedance
R
DSP
V
O
= V
DD
*(0.5)
Output Impedance
R
DSN
V
O
= V
DD
*(0.5)
Output High Voltage
V
OH
I
OH
= -8 mA
I
OL
= 8 mA
Output Low Voltage
V
OL
1
Rise Time
T
r
V
OL
= 0.8 V, V
OH
= 2.0 V
1
Fall Time
T
f
V
OH
= 2.0 V, V
OL
= 0.8 V
Stable power supply, valid clock presented
1
tLOCK
PLL Lock Time
on REF pin
1
Duty Cycle
D
t
V
T
= 1.4V;Cl=30pF
Tcyc-cyc at 66MHz , Loaded Outputs
1
Cycle to Cycle jitter
Tcyc-cyc >66MHz , Loaded Outputs
1
Absolute Jitter
Tjabs
10000 cycles; Cl=30pF
1
Jitter; 1-Sigma
Tj1s
10000 cycles; Cl=30pF
1
Skew
T
sk
V
T
= 1.4 V (Window) Output to Output
Measured at VDD/2 on the CLKOUT
1
Device to Device Skew Tdsk-Tdsk
pins of devices
1
Delay Input-Output
D
R1
V
T
= 1.4 V
1
MIN
10
10
2.4
TYP
2.9
0.25
0.8
1.0
MAX UNITS
24
Ω
24
Ω
5.0
V
0.4
V
1.5
ns
1.5
ns
1.0
ms
%
ps
ps
ps
ps
ps
ps
ps
40
50
-100
60
14
60
250
200
100
30
250
700
700
0
0
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - OUTPUT
T
A
= 0 - 70°C; V
DD
= V
DDL
= 3.3 V +/-10%; C
L
= 20 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
Output Impedance
R
DSP
V
O
= V
DD
*(0.5)
10
Output Impedance
R
DSN
V
O
= V
DD
*(0.5)
10
Output High Voltage
V
OH
I
OH
= -8 mA
2.4
I
OL
= 8 mA
Output Low Voltage
V
OL
1
Rise Time
T
r
V
OL
= 0.8 V, V
OH
= 2.0 V
1
Fall Time
T
f
V
OH
= 2.0 V, V
OL
= 0.8 V
1
Rise Time
T
r
V
OL
= 0.8 V, V
OH
= 2.0 V; 5pF
1
1
Fall Time
T
f
V
OH
= 2.0 V, V
OL
= 0.8 V; 5pF
1
Stable power supply, valid clock presented
PLL Lock Time1
tLOCK
on REF pin
D
t
V
T
= 1.4V;Cl=30pF
40
1
Duty Cycle
V
T
= Vdd/2; Fout <66.6MHz
45
D
t
Tcyc-cyc at 66MHz , Loaded Outputs
1
Cycle to Cycle jitter
Tcyc-cyc >66MHz , Loaded Outputs
1
Absolute Jitter
Tjabs
10000 cycles; Cl=30pF
-100
1
Jitter; 1-Sigma
Tj1s
10000 cycles; Cl=30pF
1
Skew
T
sk
V
T
= 1.4 V (Window) Output to Output
Measured at VDD/2 on the CLKOUT
Device to Device Skew
1
Tdsk-Tdsk
pins of devices
1
Delay Input-Output
D
R1
V
T
= 1.4 V
1
TYP
2.9
0.25
1.2
1.2
MAX UNITS
24
Ω
24
Ω
3.3
V
0.4
V
2.0
ns
2.0
ns
ns
ns
1.0
ms
%
%
ps
ps
ps
ps
ps
ps
ps
50
50
70
14
0
0
60
55
250
200
100
30
250
700
700
Guaranteed by design, not 100% tested in production.
0051L—08/03/07
4
ICS9112-17
Output to Output Skew
The skew between CLKOUT and the CLKA/B outputs is not dynamically adjusted by the PLL. Since CLKOUT is one
of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded,
zero phase difference will maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLKA/B outputs are less loaded than CLKOUT, CLKA/B outputs will lead it; and if the CLKA/B is more loaded
than CLKOUT, CLKA/B will lag the CLKOUT.
Since the CLKOUT and the CLKA/B outputs are identical, they all start at the same time, but different loads cause them
to have different rise times and different times crossing the measurement thresholds.
REF input and
all outputs
loaded
Equally
REF input and CLKA/B
outputs loaded equally, with
CLKOUT loaded
More.
REF input and CLKA/B
outputs loaded equally, with
CLKOUT loaded
Less.
0051L—08/03/07
Timing diagrams with different loading configurations
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
