Si8430/31/35
T
R I P L E
- C
H A N N E L
D
I G I TA L
I
S O L A T O R
Features
High-speed operation:
DC – 150 Mbps
Low propagation delay:
<10 ns
Wide Operating Supply Voltage:
2.375-5.5V
Low power: I1 + I2 <
12 mA/channel at 100 Mbps
Precise timing:
2 ns pulse width distortion
1 ns channel-channel matching
2 ns pulse width skew
2500 V
RMS
isolation
Transient Immunity: >25 kV/µs
Tri-state outputs with ENABLE
control
DC correct
No start-up initialization required
<10 µs Startup Time
High temperature operation:
125 °C at 100 Mbps
100 °C at 150 Mbps
Wide body SOIC-16 package
Pin Assignments
Wide Body SOIC
V
DD1
GND1
A1
A2
A3
NC
EN1/NC
GND1
1
2
3
4
5
6
7
8
Top View
16
15
14
13
12
11
10
9
V
DD2
GND2
B1
B2
B3
NC
EN2/NC
GND2
Applications
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power factor correction systems
Safety Regulatory Approvals
UL recognition:2500 V
RMS
for 1
Minute per UL1577
CSA component acceptance
notice #5A
VDE certification conformity
DIN EN 60747-5-2 (VDE0884
Part 2):2003-01
DIN EN60950(VDE0805):
2001-12;EN60950:2000
V
IORM
= 560 Vpeak
Description
Silicon Lab's family of digital isolators are CMOS devices that employ
an RF coupler to transmit digital information across an isolation
barrier. Very high speed operation at low power levels is achieved.
These parts are available in a 16-pin wide body SOIC package. Three
speed grade options (1, 10, 150 Mbps) are available and achieve
typical propagation delay of less than 10 ns.
Block Diagram
Si8430/35
Si8431
A1
A2
A3
NC
B1
B2
B3
EN2/NC
A1
A2
A3
EN1
B1
B2
B3
EN2
Rev. 0.2 10/06
Copyright © 2006 by Silicon Laboratories
Si8430/31/35
Si8430/31/35
T
A B L E O F
C
O N T E N TS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1. Supply Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2. Input and Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3. Enable (EN1, EN2) Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.4. RF Immunity and Common Mode Transient Immunity . . . . . . . . . . . . . . . . . . . . . . . 22
4.5. RF Radiated Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7. Package Outline: Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Rev. 0.2
3
Si8430/31/35
1. Electrical Specifications
Table 1. Electrical Characteristics
(V
DD1
= 5 V, V
DD2
= 5 V, T
A
= –40 to 125 ºC)
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Enable Input High Current
Enable Input Low Current
Si8430/35-A,-B,-C, V
DD1
Si8430/35-A,-B,-C, V
DD2
Si8430/35-A,-B,-C, V
DD1
Si8430/35-A,-B,-C, V
DD2
Si8431-A,-B,-C, V
DD1
Si8431-A,-B,-C, V
DD2
Si8431-A,-B,-C, V
DD1
Si8431-A,-B,-C, V
DD2
Si8430/35-B,-C, V
DD1
Si8430/35-B,-C, V
DD2
Si8431-B,-C, V
DD1
Si8431-B,-C, V
DD2
Si8430-C, V
DD1
Si8430-C, V
DD2
Si8431-C, V
DD1
Si8431-C, V
DD2
Symbol
V
IH
V
IL
V
OH
V
OL
I
L
I
ENH
I
ENL
Test Condition
Min
2.0
—
Typ
—
—
4.8
0.2
—
4
20
7
6
14
6
8
10
13
12
11
8
12
13
11
23
13
21
Max
—
0.8
—
0.4
±10
—
—
10
9
18
9
12
15
19
17
15
12
16
17
15
28
18
26
Unit
V
V
V
V
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
loh = –4 mA
lol = 4 mA
V
ENx
= V
IH
V
ENx
= V
IL
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
V
DD1
,V
DD2
– 0.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DC Supply Current
(All inputs 0 V or at Supply)
10 Mbps Supply Current
(All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
100 Mbps Supply Current
(All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
4
Rev. 0.2
Si8430/31/35
Table 1. Electrical Characteristics (Continued)
(V
DD1
= 5 V, V
DD2
= 5 V, T
A
= –40 to 125 ºC)
Parameter
Si843x-A
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
1
Pulse Width Distortion
|t
PLH
- t
PHL
|
1
Symbol
Test Condition
Timing Characteristics
Min
Typ
Max
Unit
0
—
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD/OD
25
—
—
—
0
—
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD/OD
10
—
—
—
0
—
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD/OD
4
—
—
—
—
—
40
—
—
—
—
—
20
—
—
—
—
—
6.5
—
—
—
1
1000
75
30
50
40
10
100
35
7.5
25
5
150
6.6
9.5
3
5.5
3
Mbps
ns
ns
ns
ns
ns
Mbps
ns
ns
ns
ns
ns
Mbps
ns
ns
ns
ns
ns
Propagation Delay Skew
2
Channel-Channel Skew
3
Si843x-B
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
1
Pulse Width Distortion
|t
PLH
- t
PHL
|
1
Propagation Delay Skew
2
Channel-Channel Skew
3
Si843x-C
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
1
Pulse Width Distortion
|t
PLH
- t
PHL
|
1
Propagation Delay Skew
2
Channel-Channel Skew
3
Rev. 0.2
5