PRELIMINARY DATA SHEET
MICRONAS
CDC1631F-E
Automotive Controller
Edition Aug. 2, 2004
6251-617-1PD
MICRONAS
CDC1631F-E
Contents
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Section
1.
1.1.
1.2.
1.3.
2.
2.1.
2.2.
2.3.
3.
3.1.
3.2.
3.3.
3.4.
4.
5.
5.1.
6.
6.1.
7.
7.1.
7.2.
8.
8.1.
9.
10.
Title
Introduction
Features
Abbreviations
Block Diagram
Package and Pins
Package Outline Dimensions
Pin Assignment
External Components
Electrical Data
Absolute Maximum Ratings
Recommended Operating Conditions
Characteristics
Recommended Crystal Characteristics
CPU, RAM, ROM and Banking
Core Logic
Control Register CR
Interrupt Controller (IR)
Interrupt Assignment
PRELIMINARY DATA SHEET
Hardware Options
Functional Description
Listing of Dedicated Addresses and Corresponding Hardware Options
Register Cross Reference Table
Modified Registers
Differences
Data Sheet History
2
Aug. 2, 2004; 6251-617-1PD
Micronas
1. Introduction
Release Note: Revision bars indicate significant changes to the previous edition.
The device is a microcontroller for use in automotive applications. The on-chip CPU is a 65C816, an upgrade of the 65C02 with 16-bit internal data and 24-bit address bus. The chip
consists of timer/counters, an interrupt controller, a multichannel A/D converter, a stepper motor and LCD driver, a UART and a CAN interface and PWM outputs. This document
provides ROM hardware-specific information. General information on operating the IC can be found in the document “CDC16xxF-E, Automotive Controller Family User Manual,
CDC1605F-E Automotive Controller Specification” (6251-606-1PD).
Micronas
Aug. 2, 2004; 6251-617-1PD
PRELIMINARY DATA SHEET
1.1. Features
Table 1–1:
CDC16xxF Family Feature List
This device:
Item
Core
CPU
CPU-active operation
modes
Power-saving operation
modes (CPU inactive)
EMI reduction mode
Oscillators
RAM
ROM
16-bit 65C816, featuring software compatibility with its 8-bit NMOS and CMOS 6502-series predecessors
FAST, SLOW and DEEP SLOW
WAKE and IDLE
selectable in FAST mode
4-MHz to 12-MHz quartz, RC
6 Kbyte
ROMless,
external pro-
gram storage
with up to
16 Mbyte, inter-
nal 2-Kbyte
boot ROM
✔
256-Kbyte
Flash, bottom
boot configura-
tion, internal 2-
Kbyte boot
ROM
2 Kbyte
64 Kbyte
4-MHz to 12-MHz quartz
6 Kbyte
ROMless,
external pro-
gram storage
with up to
16 Mbyte, inter-
nal 2-Kbyte
boot ROM
-
256-Kbyte
Flash, bottom
boot configura-
tion, internal 2-
Kbyte boot
ROM
2.75 Kbyte
90 Kbyte
4 Kbyte
128 Kbyte
6 Kbyte
FAST and SLOW
-
CDC1605F-E
EMU
CDC1607F-E
MCM Flash
CDC1631F-E
Mask ROM
CDC1605F-C
EMU
CDC1607F-C
MCM Flash
CDC1641F-C
Mask ROM
CDC1652F-C
Mask ROM
CDC1672F-C
Mask ROM
CDC1631F-E
216 Kbyte
Multiplier, 8 by 8 bit
3
Table 1–1:
CDC16xxF Family Feature List, continued
This device:
Item
Digital watchdog
Central clock divider
Interrupt controller
expanding NMI
Port interrupts including
slope selection
Port wake-up inputs
including slope / level
selection
Patch module
Boot system
CDC1605F-E
EMU
✔
✔
16 inputs,15 priority levels
4 inputs
10
-
CDC1607F-E
MCM Flash
CDC1631F-E
Mask ROM
CDC1605F-C
EMU
CDC1607F-C
MCM Flash
CDC1641F-C
Mask ROM
CDC1652F-C
Mask ROM
CDC1672F-C
Mask ROM
4
Aug. 2, 2004; 6251-617-1PD
CDC1631F-E
10 ROM locations
allows in-system downloading of
code and data into RAM via serial
link
5 ROM loca-
tions
-
10 ROM locations
allows in-system downloading of
code and data into RAM via serial
link
5 ROM loca-
tions
-
6 ROM locations
Analog
Reset/Alarm
Clock and supply
supervision
10-bit ADC, charge
balance type
ADC reference
Comparators
LCD
Combined input for regulator input supervision
✔
9 channels (5 channels selectable as digital input)
PRELIMINARY DATA SHEET
VREF pin
P06COMP with 1/2 AVDD reference
internal processing of all analog voltages for the LCD driver
Micronas
Table 1–1:
CDC16xxF Family Feature List, continued
This device:
Item
Communication
DMA
UART
Synchronous serial
peripheral interfaces
Full CAN modules V2.0B
1 DMA channel for serving the
graphics bus interface
3: UART0, UART1 and UART2
2: SPI0 and SPI1
3: CAN0, CAN1 and CAN2 with
256-byte object RAM each
(LCAN000F)
1 master module
-
1: UART0
1: SPI0
1: CAN0 with
256-byte object
RAM
(LCAN000F)
-
1 DMA channel for serving the
graphics bus interface
3: UART0, UART1 and UART2
2: SPI0 and SPI1
3: CAN0, CAN1 and CAN2 with
256-byte object RAM each
(LCAN0009)
1 master module
-
1: UART0
1: SPI0
1: CAN0 with
256-byte object
RAM
(LCAN0009)
-
1 DMA channel for serving the
graphics bus interface
3: UART0, UART1 and UART2
2: SPI0 and SPI1
2: CAN0 and CAN1 with 256-byte
object RAM each (LCAN0009)
CDC1605F-E
EMU
CDC1607F-E
MCM Flash
CDC1631F-E
Mask ROM
CDC1605F-C
EMU
CDC1607F-C
MCM Flash
CDC1641F-C
Mask ROM
CDC1652F-C
Mask ROM
CDC1672F-C
Mask ROM
Micronas
Aug. 2, 2004; 6251-617-1PD
PRELIMINARY DATA SHEET
DIGITbus
Input & Output
Universal ports select-
able as 4:1-mux LCD
segment/backplane lines
or digital I/O ports
Universal port slew rate
Stepper motor control
modules with high current
ports
8-bit PWM modules
1 master module
up to 52 I/O or 48 LCD segment lines (=192 segments),
in groups of two, configurable as I/O or LCD
HW-preselectable
5 modules, 24 dI/dt-controlled ports
5 modules: PWM0, PWM1,
PWM2, PWM3 and PWM4
✔
2
3 modules:
PWM0, PWM1,
PWM2
5 modules: PWM0, PWM1,
PWM2, PWM3 and PWM4
2 modules:
PWM0, PWM1
5 modules: PWM0, PWM1,
PWM2, PWM3 and PWM4
CDC1631F-E
Audio module with auto-
decay
SW-selectable clock out-
puts
Polling/flash timer output
1 high current port output operable in power-saving
operation modes
-
5
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