CAT93C66, CAT93W66
4 kb Microwire Serial CMOS
EEPROM
Description
The CAT93C66 is a 4 kb CMOS Serial EEPROM device which is
organized as either 256 registers of 16 bits (ORG pin at V
CC
) or 512
registers of 8 bits (ORG pin at GND). The CAT93W66 features x16
memory organization only. Each register can be written (or read)
serially by using the DI (or DO) pin. The device features sequential
read and self−timed internal write with auto−clear. On−chip
Power−On Reset circuitry protects the internal logic against powering
up in the wrong state.
Features
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SOIC−8
V, W* SUFFIX
CASE 751BD
UDFN−8
HU4 SUFFIX
CASE 517AZ
TDFN−8*
VP2 SUFFIX
CASE 511AK
•
•
•
•
•
•
•
•
•
•
•
•
High Speed Operation: 4 MHz (5 V), 2 MHz (1.8 V)
1.8 V to 5.5 V Supply Voltage Range
Selectable x8 or x16 Memory Organization: CAT93C66
Self−timed Write Cycle with Auto−clear
Sequential Read
Software Write Protection
Power−up Inadvertent Write Protection
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Ranges
8−lead PDIP, SOIC, TSSOP, 6−lead SOT−23, 8−pad TDFN and
UDFN Packages
•
These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
V
CC
V
CC
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
SOIC−8
X SUFFIX
CASE 751BE
SOT23−6
TB SUFFIX
CASE 527AJ
PIN CONFIGURATION
CS
SK
DI
DO
1
2
3
4
8 V
CC
7 NC
6 ORG
5 GND
NC
V
CC
CS
SK
1
2
3
4
8 ORG
7 GND
6 DO
5 DI
ORG
CS
SK
DI
CAT93C66
DO
CS
SK
DI
CAT93W66
DO
PDIP (L), SOIC (V, X),
TSSOP (Y), TDFN (VP2)*,
UDFN (HU4)
CS
SK
DI
DO
1
2
3
4
8 V
CC
7 NC
6 NC
5 GND
SOIC (W)*
DO
GND
DI
1
2
3
6 V
CC
5 CS
4 SK
GND
GND
SOT−23 (TB)**
Figure 1. Functional Symbols
CAT93C66 Selectable Organization:
TDFN (VP2)
CAT93W66
* Not recommended for new designs
** CAT93C66 available in SOT−23 6−pin for x8
Organization. Contact factory for availability.
When the ORG pin is connected to V
CC
, the x16 organization is
selected. When it is connected to ground, the x8 organization is
selected. If the ORG pin is left unconnected, then an internal pull−up
device will select the x16 organization.
CAT93W66:
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
The device works in x16 mode only.
©
Semiconductor Components Industries, LLC, 2012
April, 2012
−
Rev. 11
1
Publication Order Number:
CAT93C66/D
CAT93C66, CAT93W66
Table 1. PIN FUNCTION
Pin Name
CS
SK
DI
DO
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
Pin Name
V
CC
GND
ORG (Note 1)
NC
Function
Power Supply
Ground
Memory Organization
No Connection
1. ORG Pin available for the CAT93C66 only.
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 2)
Ratings
−65
to +150
−0.5
to +6.5
Units
°C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. The DC input voltage on any pin should not be lower than
−0.5
V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than
−1.5
V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 3. RELIABILITY CHARACTERISTICS
(Note 3)
Symbol
N
END
(Note 4)
T
DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
3. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
4. Block Mode, V
CC
= 5 V, 25°C.
Table 4. D.C. OPERATING CHARACTERISTICS
−
MATURE PRODUCT
(
V
CC
= +1.8 V to +5.5 V, T
A
=
−40°C
to +125°C unless otherwise specified.)
Symbol
I
CC1
I
CC2
I
SB1
I
SB2
I
LI
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Power Supply Current
(Write)
Power Supply Current
(Read)
Power Supply Current
(Standby) (x8 Mode)
Power Supply Current
(Standby) (x16 Mode)
Input Leakage Current
f
SK
= 1 MHz, V
CC
= 5.0 V
f
SK
= 1 MHz, V
CC
= 5.0 V
V
IN
= GND or V
CC
,
CS = GND ORG = GND
V
IN
= GND or V
CC
, CS = GND
ORG = Float or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
,
CS = GND
4.5 V
≤
V
CC
< 5.5 V
4.5 V
≤
V
CC
< 5.5 V
1.8 V
≤
V
CC
< 4.5 V
1.8 V
≤
V
CC
< 4.5 V
4.5 V
≤
V
CC
< 5.5 V, I
OL
= 2.1 mA
Test Conditions
Min
Max
1
500
Units
mA
mA
mA
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
−0.1
2
0
V
CC
x 0.7
2.4
2
4
1
2
1
2
1
2
0.8
V
CC
+ 1
V
CC
x 0.2
V
CC
+ 1
0.4
mA
mA
Output Leakage Current
mA
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
V
V
V
V
V
V
4.5 V
≤
V
CC
< 5.5 V, I
OH
=
−400
mA
1.8 V
≤
V
CC
< 4.5 V, I
OL
= 1 mA
1.8 V
≤
V
CC
< 4.5 V, I
OH
=
−100
mA
0.2
V
CC
−
0.2
V
V
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CAT93C66, CAT93W66
Table 5. D.C. OPERATING CHARACTERISTICS
−
NEW PRODUCT (REV H)
(V
CC
= +1.8 V to +5.5 V, T
A
=−40°C to +125°C unless otherwise specified.)
Symbol
I
CC1
I
CC2
I
SB1
I
SB2
Parameter
Supply Current (Write)
Supply Current (Read)
Standby Current
(x8 Mode)
Standby Current
(x16 Mode)
Input Leakage Current
Write, V
CC
= 5.0 V
Read, DO open, f
SK
= 2 MHz, V
CC
= 5.0 V
V
IN
= GND or V
CC
CS = GND, ORG = GND
V
IN
= GND or V
CC
CS = GND,
ORG = Float or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
CS = GND
4.5 V
≤
V
CC
< 5.5 V
4.5 V
≤
V
CC
< 5.5 V
1.8 V
≤
V
CC
< 4.5 V
1.8 V
≤
V
CC
< 4.5 V
4.5 V
≤
V
CC
< 5.5 V, I
OL
= 3 mA
4.5 V
≤
V
CC
< 5.5 V, I
OH
=
−400
mA
1.8 V
≤
V
CC
< 4.5 V, I
OL
= 1 mA
1.8 V
≤
V
CC
< 4.5 V, I
OH
=
−100
mA
V
CC
−
0.2
2.4
0.2
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Output Leakage
Current
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
−0.1
2
0
V
CC
x 0.7
Test Conditions
Min
Max
1
500
2
5
1
3
1
2
1
2
0.8
V
CC
+ 1
V
CC
x 0.2
V
CC
+ 1
0.4
V
V
V
V
V
V
V
V
mA
mA
mA
Units
mA
mA
mA
I
LI
Table 6. PIN CAPACITANCE
(T
A
= 25°C, f = 1.0 MHz, V
CC
= +5.0 V)
Symbol
C
OUT
(Note 5)
C
IN
(Note 5)
Test
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Conditions
V
OUT
= 0 V
V
IN
= 0 V
Min
Typ
Max
5
5
Units
pF
pF
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 7. POWER−UP TIMING
(Notes 6, 7)
Symbol
t
PUR
t
PUW
Power−up to Read Operation
Power−up to Write Operation
Parameter
Max
1
1
Units
ms
ms
6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
7. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Table 8. A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
≤
50 ns
0.4 V to 2.4 V
0.8 V, 2.0 V
0.2 V
CC
to 0.7 V
CC
0.5 V
CC
Current Source I
OLmax
/I
OHmax
; CL = 100 pF
4.5 V
≤
V
CC
≤
5.5 V
4.5 V
≤
V
CC
≤
5.5 V
1.8 V
≤
V
CC
≤
4.5 V
1.8 V
≤
V
CC
≤
4.5 V
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CAT93C66, CAT93W66
Table 9. A.C. CHARACTERISTICS
−
MATURE PRODUCT
(V
CC
= +1.8 V to +5.5 V, T
A
=
−40°C
to +125°C, unless otherwise specified.) (Note 8)
Limits
Symbol
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ
(Note 9)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High−Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
DC
0.25
0.25
0.25
0.25
2000
Parameter
Min
50
0
100
100
0.25
0.25
100
5
Max
Units
ns
ns
ns
ns
ms
ms
ns
ms
ms
ms
ms
ms
kHz
8. Test conditions according to “A.C. Test Conditions” table.
9. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
Table 10. A.C. CHARACTERISTICS
−
NEW PRODUCT (Rev H)
(V
CC
= +1.8 V to +5.5 V, TA =
−40°C
to +125°C, unless otherwise specified.)
V
CC
= 1.8 V
−
5.5 V
Symbol
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ
(Note 10)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High−Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
DC
0.25
0.25
0.25
0.25
2000
DC
Parameter
Min
50
0
100
100
0.25
0.25
100
5
0.1
0.1
0.1
0.1
4000
Max
V
CC
= 4.5 V
−
5.5 V
Min
50
0
50
50
0.1
0.1
100
5
Max
Units
ns
ns
ns
ns
ms
ms
ns
ms
ms
ms
ms
ms
kHz
10. This parameter is tested initially and after a design or process change that affects the parameter.
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CAT93C66, CAT93W66
Device Operation
The CAT93C66 is a 4096−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93C66 can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 11−bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
12−bit instructions control the reading, writing and erase
operations of the device. The CAT93W66 works in x16
mode only. The device operates on a single power supply
and will generate on chip, the high voltage required during
any write operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation. The serial communication protocol
follows the timing shown in Figure 2.
Table 11. INSTRUCTION SET
Address
Instruction
READ
ERASE
WRITE
EWEN
EWDS
ERAL
WRAL
Start Bit
1
1
1
1
1
1
1
Opcode
10
11
01
00
00
00
00
x8
(Note 11)
A8−A0
A8−A0
A8−A0
11XXXXXXX
00XXXXXXX
10XXXXXXX
01XXXXXXX
x16
A7−A0
A7−A0
A7−A0
11XXXXXX
00XXXXXX
10XXXXXX
01XXXXXX
D7−D0
D15−D0
D7−D0
D15−D0
Data
x8
(Note 11)
x16
Comments
Read Address AN – A0
Clear Address AN – A0
Write Address AN – A0
Write Enable
Write Disable
Clear All Addresses
Write All Addresses
The ready/busy status can be determined after the start of
internal write cycle by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the rising edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 8−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organizations).
The instruction format is shown in Instruction Set table.
11. The x8 memory organization is available for the CAT93C66 only.
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