SPANSION
Data Sheet
TM
Flash Memory
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
TM
product. Future routine
revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20846-7E
FLASH MEMORY
CMOS
16M (2M
×
8/1M
×
16) BIT
MBM29LV160T
-80/-90/-12
/MBM29LV160B
-80/-90/-12
■
GENERAL DESCRIPTION
The MBM29LV160T/B is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words
of 16 bits each. The MBM29LV160T/B is offered in a 48-pin TSOP (1), 48-pin CSOP and 48-ball FBGA packages.
The device is designed to be programmed in-system with the standard system 3.0 V V
CC
supply. 12.0 V V
PP
and
5.0 V V
CC
are not required for write or erase operations. The device can also be reprogrammed in standard EPROM
programmers.
The standard MBM29LV160T/B offers access times of 80 ns and 120 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
The MBM29LV160T/B is pin and command set compatible with JEDEC standard E
2
PROMs. Commands are
written to the command register using standard microprocessor write timings. Register contents serve as input
to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out of the device is similar
to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29LV160T/B is programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the device automatically times the erase pulse widths and
verifies proper cell margins.
(Continued)
Part No.
V
CC
= 3.3 V
Ordering Part No.
V
CC
= 3.0 V
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
+0.3 V
–0.3 V
+0.6 V
–0.3 V
■
PRODUCT LINE UP
MBM29LV160T/160B
-80
—
80
80
30
—
-90
90
90
35
—
-12
120
120
50
Retired Product DS05-20846-7E_July 26, 2007
MBM29LV160T
-80/-90/-12
/MBM29LV160B
-80/-90/-12
(Continued)
Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29LV160T/B is erased when shipped from the factory.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
,
by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once the end of a program or erase cycle has been
comleted, the device internally resets to the read mode.
The MBM29LV160T/B also has a hardware RESET pin. When this pin is driven low, execution of any Embedded
Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the
read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during
the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read
mode and will have erroneous data stored in the address locations being programmed or erased. These locations
need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up
firmware from the Flash memory.
Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The MBM29LV160T/B memory electrically erases all bits within
a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a
time using the EPROM programming mechanism of hot electron injection.
■
FEATURES
• Single 3.0 V read, program and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E
2
PROMs
• Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP (1) (Package suffix: PFTN-Normal Bend Type, PFTR-Reversed Bend Type)
48-pin CSOP (Package suffix: PCV)
48-ball FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
80 ns maximum access time
• Sector erase architecture
One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode
One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded Erase
TM
* Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded program
TM
* Algorithms
Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
(Continued)
Retired Product DS05-20846-7E_July 26, 2007
5
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