MBM29DL64DF
-70
Data Sheet
(Retired Product)
MBM29DL64DF
-70
Cover Sheet
This product has been retired and is not recommended for new designs. Availability of this document is retained for reference
and historical purposes only.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been
made are the result of normal data sheet improvement and are noted in the document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number
MBM29DL64DF
Revision
DS05-20905-3E
Issue Date
August 3, 2007
Data
Sheet
(R etired
Produ ct)
This page left intentionally blank.
2
MBM29DL64DF_DS05-20905-3E August 3, 2007
SPANSION
Data Sheet
TM
Flash Memory
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
TM
product. Future routine
revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20905-3E
FLASH MEMORY
CMOS
64 M (8 M
×
8/4 M
×
16) BIT
Dual Operation
MBM29DL64DF
-70
■
DESCRIPTION
MBM29DL64DF is a 64 M-bit, 3.0 V-only Flash memory organized as 8 Mbytes of 8 bits each or 4 M words of 16
bits each. The device comes in 48-pin TSOP (1) and 48-ball FBGA packages. This device is designed to be
programmed in system with 3.0 V V
CC
supply. 12.0 V V
PP
and 5.0 V V
CC
are not required for write or erase operations.
The device can also be reprogrammed in standard EPROM programmers.
The device is organized into four physical banks : Bank A, Bank B, Bank C and Bank D, which are considered to
be four separate memory arrays operations. This device is the almost identical to Fujitsu’s standard 3 V only Flash
memories, with the additional capability of allowing a normal non-delayed read access from a non-busy bank of
the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the
other bank.
(Continued)
Part No.
Power Supply Voltage V
CC
(V)
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
MBM29DL64DF-70
+0.6
V
3.0 V
−0.3
V
■
PRODUCT LINE UP
70
70
30
■
PACKAGES
48-pin plastic TSOP (1)
Marking Side
48-ball plastic FBGA
(FPT-48P-M19)
(BGA-48P-M13)
Retired Product DS05-20905-3E_August 3, 2007
MBM29DL64DF
-70
(Continued)
The new design concept called FlexBank
TM
*
1
Architecture is implemented. With this concept the device can
execute simultaneous operation between Bank 1, a bank chosen from among the four banks, and Bank 2, a
bank consisting of the three remaining banks. This means that any bank can be chosen as Bank 1. (Refer to
■FUNCTIONAL
DESCRIPTION for Simultaneous Operation.)
The standard device offers access times 70 ns, allowing operation of high-speed microprocessors without the
wait. To eliminate bus contention the device has separate chip enable (CE) , write enable (WE) and output enable
(OE) controls.
This device supports pin and command set compatible with JEDEC standard E
2
PROMs. Commands are written
to the command register using standard microprocessor write timings. Register contents serve as input to an
internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out of the device is similar
to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The device is programmed by executing the program command sequence. This invokes the Embedded Program
Algorithm
TM
which is an internal algorithm that automatically times the program pulse widths and verifies proper
cell margin. Typically each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished
by executing the erase command sequence. This invokes the Embedded Erase Algorithm
TM
which is an internal
algorithm that automatically preprograms the array if it is not already programmed before executing the erase
operation. During erase, the device automatically times the erase pulse widths and verifies the proper cell margin.
Each sector is typically erased and verified in 0.5 second (if already completely preprogrammed) .
The device also features sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The device is erased when shipped from the factory.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
,
by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once the end of a program or erase cycle is completed,
the device internally returns to the read mode.
The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program
Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read
mode. The RESET pin may be tied to the system reset circuitry. Therefore if a system reset occurs during the
Embedded Program
TM
*
2
Algorithm or Embedded Erase
TM
*
2
Algorithm, the device is automatically reset to the
read mode and have erroneous data stored in the address locations being programmed or erased. These
locations need rewriting after the reset. Resetting the device enables the system’s microprocessor to read the
boot-up firmware from the Flash memory.
Fujitsu Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The device memory electrically erases the entire chip or all
bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/
word at a time using the EPROM programming mechanism of hot electron injection.
*1 : FlexBank
TM
is a trademark of Fujitsu Limited.
*2 : Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
Retired Product DS05-20905-3E_August 3, 2007
5
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