CY7C1347F
4-Mb (128K x 36) Pipelined Sync SRAM
Features
• Fully registered inputs and outputs for pipelined oper-
ation
• 128K by 36 common I/O architecture
• 3.3V core power supply
• 2.5V/3.3V I/O operation
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.6 ns (for 225-MHz device)
— 2.8 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
— 4.5 ns (for 100-MHz device)
• User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100-pin TQFP, 119-pin BGA and
165-pin fBGA packages
• “ZZ” Sleep Mode option and Stop Clock option
• Available in Industrial and Commercial temperature
ranges
Functional Description
[1]
The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined
SRAM designed to support zero-wait-state secondary cache
with minimal glue logic.
CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V
level, the I/O pins are 3.3V tolerant when V
DDQ
= 2.5V.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise is 2.6 ns (250-MHz
device)
CY7C1347F supports either the interleaved burst sequence
used by the Intel Pentium processor or a linear burst sequence
used by processors such as the PowerPC
®
. The burst
sequence is selected through the MODE pin. Accesses can be
initiated by asserting either the Address Strobe from
Processor (ADSP) or the Address Strobe from Controller
(ADSC) at clock rise. Address advancement through the burst
sequence is controlled by the ADV input. A 2-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the
rest of the burst access.
Byte write operations are qualified with the four Byte Write
Select (BW
[A:D]
) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to provide
proper data during depth expansion, OE is masked during the
first clock of a read cycle when emerging from a deselected
state.
Logic Block Diagram
A0, A1, A
ADDRESS
REGISTER
2
A
[1:0]
MODE
ADV
CLK
Q1
ADSC
ADSP
BW
D
DQ
D ,
DQP
D
BYTE
WRITE REGISTER
DQ
C ,
DQP
C
BYTE
WRITE REGISTER
DQ
B ,
DQP
B
BYTE
WRITE REGISTER
DQ
A ,
DQP
A
BYTE
WRITE REGISTER
BURST
COUNTER
CLR
AND
Q0
LOGIC
DQ
D
,DQP
D
BYTE
WRITE DRIVER
DQ
C ,
DQP
C
BYTE
WRITE DRIVER
DQ
B ,
DQP
B
BYTE
WRITE DRIVER
DQ
A ,
DQP
A
BYTE
WRITE DRIVER
BW
C
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
BW
B
DQs
DQP
A
DQP
B
DQP
C
DQP
D
BW
A
BWE
GW
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
PIPELINED
ENABLE
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05213 Rev. *C
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised January 13, 2004
CY7C1347F
Selection Guide
-250
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
2.6
325
40
-225
2.6
290
40
-200
2.8
265
40
-166
3.5
240
40
-133
4.0
225
40
-100
4.5
205
40
Unit
ns
mA
mA
Shaded areas contain advance information. Please contact your local Cypress Sales representative for availability of these parts.
Pin Configurations
100-Pin TQFP
A
A
CE
1
CE
2
BW
D
BW
C
BW
B
BW
A
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
DQP
C
DQ
C
DQ
C
V
DDQ
V
SSQ
DQ
C
DQ
C
DQ
C
DQ
C
V
SSQ
V
DDQ
DQ
C
DQ
C
NC
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SSQ
DQ
D
DQ
D
DQ
D
DQ
D
V
SSQ
V
DDQ
DQ
D
DQ
D
DQP
D
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
BYTE C
BYTE D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1347F
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQP
B
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SSQ
DQ
A
DQ
A
DQ
A
DQ
A
V
SSQ
V
DDQ
DQ
A
DQ
A
DQP
A
BYTE B
BYTE A
Document #: 38-05213 Rev. *C
MODE
A
A
A
A
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Page 2 of 19
CY7C1347F
Pin Configurations
(continued)
119-Ball BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
C
DQ
C
V
DDQ
DQ
C
DQ
C
V
DDQ
DQ
D
DQ
D
V
DDQ
DQ
D
DQ
D
NC
NC
V
DDQ
2
A
CE
2
A
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
A
NC
NC
3
A
A
A
V
SS
V
SS
V
SS
BW
C
V
SS
NC
V
SS
BW
D
V
SS
V
SS
V
SS
MODE
A
NC
4
ADSP
ADSC
V
DD
NC
CE
1
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
V
DD
A
NC
5
A
A
A
V
SS
V
SS
V
SS
BW
B
V
SS
NC
V
SS
BW
A
V
SS
V
SS
V
SS
NC
A
NC
6
A
CE
3
A
DQP
B
DQ
B
DQ
B
DQ
B
DQ
B
V
DD
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
A
NC
NC
7
V
DDQ
NC
NC
DQ
B
DQ
B
V
DDQ
DQ
B
DQ
B
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
NC
ZZ
V
DDQ
165-Ball fBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
NC
MODE
2
A
A
NC
DQ
C
DQ
C
DQ
C
DQ
C
V
SS
DQ
D
DQ
D
DQ
D
DQ
D
NC
NC
NC
3
CE1
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
4
BW
C
BW
D
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
5
BW
B
BW
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
NC
NC
6
CE
1
CLK
7
BWE
GW
8
ADSC
OE
9
ADV
ADSP
10
A
A
NC
DQ
B
DQ
B
DQ
B
DQ
B
NC
DQ
A
DQ
A
DQ
A
DQ
A
NC
A
A
11
NC
NC
DQP
B
DQ
B
DQ
B
DQ
B
DQ
B
ZZ
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
NC
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
A0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
Document #: 38-05213 Rev. *C
Page 3 of 19
CY7C1347F
Pin Definitions
(BGA,FBGA)
Name
(100TQFP)
Name
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Description
Address Inputs used to select one of the 128K address locations.
Sampled at
the rising edge of the CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are sampled active. A
[1:0]
feeds the 2-bit counter.
Byte Write Select Inputs, active LOW.
Qualified with BWE to conduct byte writes
to the SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW.
When asserted LOW on the rising edge
of CLK, a global write is conducted (ALL bytes are written, regardless of the values
on BW
[A:D]
and BWE).
Byte Write Enable Input, active LOW.
Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
Clock Input.
Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW.
Sampled on the rising edge of CLK. Used in
conjunction with CE
2
and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH.
Chip Enable 2 Input, active HIGH.
Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW.
Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
2
to select/deselect the device.
A
0,
A
1,
A
BW
A,
BW
B,
BW
C,
BW
D
GW
A
[16:0]
BW
[A:D]
GW
BWE
CLK
CE
1
CE
2
CE
3
OE
BWE
CLK
CE
1
CE
2
CE
3
OE
Input-
Output Enable, asynchronous input, active LOW.
Controls the direction of the
Asynchronous I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O
pins are three-stated, and act as input data pins. OE is masked during the first clock
of a read cycle when emerging from a deselected state.
Input-
Synchronous
Input-
Synchronous
Advance Input signal, sampled on the rising edge of CLK.
When asserted, it
automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK.
When
asserted LOW, addresses presented to the device are captured in the address
registers. A
[1:0]
are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized. ASDP is ignored when CE
1
is deasserted
HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK.
When
asserted LOW, addresses presented to the device are captured in the address
registers. A
[1:0]
are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized.
ADV
ADSP
ADV
ADSP
ADSC
ADSC
Input-
Synchronous
ZZ
ZZ
Input-
ZZ “sleep” Input.
This active HIGH input places the device in a non-time-critical
Asynchronous “sleep” condition with data integrity preserved. For normal operation, this pin has
to be LOW or left floating. ZZ pin has an internal pull-down.
I/O-
Synchronous
Bidirectional Data I/O lines.
As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses presented during the previous
clock rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPs are
placed in a three-state condition.
Power supply inputs to the core of the device.
Ground for the core of the device.
Power supply for the I/O circuitry.
Ground for the I/O circuitry.
Selects Burst Order.
When tied to GND selects linear burst sequence. When tied
to V
DDQ
or left floating selects interleaved burst sequence. This is a strap pin and
should remain static during device operation. Mode Pin has an internal pull-up.
No Connects.
Page 4 of 19
DQ
A,
DQ
B
DQs
DQ
C,
DQ
D
DQPs
DQP
A,
DQP
B,
DQP
C,
DQP
D
V
DD
V
SS
V
DDQ
V
SSQ
MODE
V
DD
V
SS
V
DDQ
V
SSQ
MODE
Power Supply
Ground
I/O Power
Supply
I/O Ground
Input-
Static
NC
NC
Document #: 38-05213 Rev. *C
CY7C1347F
Introduction
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (T
CO
) is 2.6 ns
(250-MHz device).
The CY7C1347F supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
linear burst sequence is suited for processors that utilize a
linear burst sequence. The burst order is user selectable, and
is determined by sampling the MODE input. Accesses can be
initiated with either the Address Strobe from Processor
(ADSP) or the Address Strobe from Controller (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
[A:D]
) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE
1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE
1
, CE
2
, CE
3
are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE
1
is HIGH. The address presented to the address inputs (A
[16:0]
)
is stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the Output Register and onto
the data bus within 2.6 ns (250-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE
1
, CE
2
, CE
3
are all asserted active. The address presented
to A
[16:0]
is loaded into the Address Register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BW
[A:D]
) and ADV inputs are
ignored during this first cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs and DQPs inputs is written into the
Document #: 38-05213 Rev. *C
corresponding address location in the RAM core. If GW is
HIGH, then the write operation is controlled by BWE and
BW
[A:D]
signals. The CY7C1347F provides byte write
capability that is described in the Write Cycle Description table.
Asserting the Byte Write Enable input (BWE) with the selected
Byte Write (BW
[A:D]
) input will selectively write to only the
desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1347F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQs and DQPs inputs. Doing so will three-state the
output drivers. As a safety precaution, DQs and DQPs are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE
1
, CE
2
, CE
3
are all asserted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BW
[A:D]
) are asserted active to conduct a write to
the desired byte(s). ADSC-triggered write accesses require a
single clock cycle to complete. The address presented to
A
[16:0]
is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global write is
conducted, the data presented to the DQs and DQPs is written
into the corresponding address location in the RAM core. If a
byte write is conducted, only the selected bytes are written.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1347F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQs and DQPs inputs. Doing so will three-state the
output drivers. As a safety precaution, DQs and DQPs are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Burst Sequences
The CY7C1347F provides a two-bit wraparound counter, fed
by A
[1:0]
, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user-selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
1
, CE
2
, CE
3
, ADSP, and ADSC must
remain inactive for the duration of t
ZZREC
after the ZZ input
returns LOW.
Page 5 of 19
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