Standard Products
UT54LVDM328 Octal 400 Mbps Bus LVDS Repeater
Data Sheet
March 5, 2002
FEATURES
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400.0 Mbps low jitter fully differential data path
200MHz clock channel
3.3 V power supply
10mA LVDS output drivers
Cold sparing all pins
Fast propagation delay of 3.5ns max
Receiver input threshold < + 100 mV
Radiation-hardened design; total dose irradiation testing to
MIL-STD-883 Method 1019
- Total-dose: 300 krad(Si) and 1 Mrad(Si)
INTRODUCTION
The UT54LVDM328 is an Octal Bus Repeater utilizing Low
Voltage Differential Signaling (LVDS) technology for low
power, high speed operation. Data paths are fully differential
from input to output for low noise generation and low pulse
width distortion. LVDS I/O enable high speed data transmission
for point-to point or multi-drop interconnects. This device is
designed for use as a high speed differential repeater.
The UT54LVDM328 is a repeater designed specifically for the
bridging of multiple backplanes in a system. The
UT54LVDM328 utilizes low voltage differential signaling to
deliver high speed while consuming minimal power with
reduced EMI. The UT54LVDM328 repeats signals between
backplanes and accepts or drives signals onto the local bus.
The individual LVDS outputs can be put into Tri-State by use
of the enable pins.
All pins have Cold Spare buffers. These buffers will be high
impedance when V
DD
is tied to V
SS
.
- Latchup immune (LET > 100 MeV-cm
2
/mg)
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Packaging options:
- 48-lead flatpack
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Standard Microcircuit Drawing 5962-01536
- QML Q and V compliant part
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Compatible with ANSI/TIA/EIA 644-1995 LVDS
Standard
END
IN1+
IN1-
+
-
OUT1+
OUT1-
IN2+
IN2-
+
-
OUT2+
OUT2-
Figure 1a. UT54LVDM328 Repeater Block Diagram
(Partial - see Page 2 for complete diagram)
1
APPLICATIONS INFORMATION
The UT54LVDM328 provides the basic bus repeater
function. The device operates as a 9 channel LVDS buffer.
Repeating the signal restores the LVDS amplitude, allowing
it to drive another media segment. This allows for isolation
of segments or long distance applications.
The intended application of these devices and signaling
technique is for both point-to-point baseband (single
termination) and multipoint (double termination) data
transmissions over controlled impedance media. The
transmission media may be printed-circuit board traces,
backplanes, or cables. (Note: The ultimate rate and distance
of data transfer is dependent upon the attenuation
characteristics of the media, the noise coupling to the
environment, and other application specific characteristics.)
Input Fail-Safe:
The UT54LVDM328 also supports OPEN, shorted and
terminated input fail-safe. Receiver output will be HIGH for
all fail-safe conditions.
PCB layout and Power System Bypass:
Circuit board layout and stack-up for the UT54LVDM328
should be designed to provide noise-free power to the device.
Good layout practice also will separate high frequency or high
level inputs and outputs to minimize unwanted stray noise
pickup, feedback and interference. Power system
performance may be greatly improved by using thin
dielectrics (4 to 10 mils) for power/ground sandwiches. This
increases the intrinsic capacitance of the PCB power system
which improves power supply filtering, especially at high
frequencies, and makes the value and placement of external
bypass capacitors less critical. External bypass capacitors
should include both RF ceramic and tantalum electrolytic
types. RF capacitors may use values in the range 0.01µF to
0.1µ F. Tantalum capacitors may be in the range of 2.2µF to
10µF. Voltage rating for tantalum capacitors should be at
least 5X the power supply voltage being used. It is
recommended practice to use two vias at each power pin of
the UT54LVDM328, as well as all RF bypass capacitor
terminals. Dual vias reduce the interconnect inductance and
extends the effective frequency range of the bypass
components.
The outer layers of the PCB may be flooded with additional
ground plane. These planes will improve shielding and
isolation, as well as increase the intrinsic capacitance of the
power supply plane system. Naturally, to be effective, these
planes must be tied to the ground supply plane at frequent
intervals with vias. Frequent via placement also improves
signal integrity in signal transmission lines by providing short
paths for image currents which reduces signal distortion. The
planes should be pulled back from all transmission lines and
component mounting pads a distance equal to the width of
the widest transmission line from the internal power or
ground plane(s) whichever is greater. Doing so minimizes
effects on transmission line impedances and reduces
unwanted parasitic capacitances at component mounting
pads.
Compatibility with LVDS standard:
In backplane multidrop configurations, with closely spaced
loads, the effective differential impedance of the line is
reduced. If the mainline has been designed for 50Ω
differential impedance, the loading effects may reduce this
to the 35Ω range depending upon spacing and capacitance
load. Terminating the line with a 35Ω load is a better match
than with 50Ω and reflections are reduced.
4
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD
V
I/O
T
STG
P
D
T
J
Θ
JC
I
I
PARAMETER
DC supply voltage
Voltage on any pin
Storage temperature
Maximum power dissipation
Maximum junction temperature
2
Thermal resistance, junction-to-case
3
DC input current
LIMITS
-0.3 to 4.0V
-0.3 to (V
DD
+ 0.3V)
-65 to +150°C
800mW
+150°C
22°C/W
±
10mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and life test .
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
T
C
V
IN
PARAMETER
Positive supply voltage
Case temperature range
DC input voltage, receiver inputs
DC input voltage, logic inputs
LIMITS
3.3 to 3.6V
-55 to +125°C
0 to 2.4V
0 to V
DD
for END or ENCK
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