VS-709
Dual Frequency VCSO
VS-709
Description
The VS-709 is a Voltage Controlled SAW Oscillator that operates at the fundamental frequency from one of the two internal
SAW filters. The SAW filters are high-Q Quartz devices that enable the circuit to achieve low phase jitter performance over a
wide operating temperature range. A divider circuit is deployed for output frequencies less than 600 MHz. The selectable dual
oscillator is housed in a hermetically sealed leadless surface mount package and offered on tape and reel. It has a tri-state
Frequency Select function that provides one of three conditions: Frequency 1, Output Disable, or Frequency 2.
Features
•
•
Industry Standard Package, 5.0 x 7.0 x 1.8 mm
5th Generation ASIC Technology for Ultra Low Jitter
120 fs-rms (fN = 622.08 MHz, 12 kHz to 20 MHz)
105 fs-rms (fN = 622.08 MHz, 50 kHz to 80 MHz)
•
•
•
•
•
•
Output Frequencies from 150 MHz to 1000 MHz
Spurious Suppression, 90 dBc Typical
2.5V or 3.3V Supply Voltage
LVPECL or LVDS Output Configurations
Tri-State Frequency Select (F1, OD, F2)
Compliant to EC RoHS6 Directive
•
•
•
•
•
•
•
Applications
PLL circuits for clock smoothing and frequency translation
Description
Standard
SONET / SDH
OTN (Optical Transport Network)
10 GbE (Gigabit Ethernet)
10 GFC (Gigabit Fibre Channel)
40 GbE & 100 GbE
Synchronous Ethernet
WiMax
GR-253-CORE
ITU-T G.709/Y.1331
IEEE 802.3ae
INCITS 364-2003
IEEE 802.3ba
ITU-T G.8261
IEEE 802.16
Block Diagram
Page1 of 9
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev: 06Aug2011
VS-709 Dual Frequency VCSO
Performance Specifications
Electrical Performance
Parameter
Nominal Frequency
1, 2, 3
Absolute Pull Range
1, 2, 3, 9
Linearity
2, 4, 9
Gain Transfer
2, 9
Temperature Stability
1, 7
Symbol
f
N
APR
Lin
Min
Frequency
150
±50
Typical
Maximum
1000
Units
MHz
ppm
%
ppm/V
ppm
±7
+445
±100
K
V
f
STAB
Supply
V
CC
I
CC
I
CC
2.97
Voltage (± 10%)
2, 3
Current (Typical 50Ω Load)
3
Current (No Load)
3
Mid Level
2, 3
Single Ended Swing
2, 3
Differential Swing
2, 3
Current
7
Rise Time
6, 7
Fall Time
6, 7
Symmetry
2, 3
Spurious Suppression
7
Jitter (600 < f
N
< 1000)
7, 8
Jitter (300 < f
N
< 500)
7, 8
Jitter (150 < f
N
< 250)
7, 8
Input Impedance (F1 or F2 Enabled)
7
Input Impedance (Output Disabled)
7
Modulation Bandwidth
7
Operating Temperature
1, 3
Package Size
1]
2]
3]
4]
5]
6]
7]
8]
3.3
73
60
3.63
V
mA
75
mA
mV
mV-pp
V-pp
Outputs
V
CC
-1.5
V
CC
-1.3
750
1.5
V
CC
-1.1
I
OUT
t
R
t
F
SYM
фJ
фJ
фJ
45
85
180
180
50
90
150
190
280
20
250
250
55
mA
ps-pp
ps-pp
%
dBc
fs-rms
fs-rms
fs-rms
Control Voltage
Z
C
Z
C
BW
123
472
200
-40
5.0 x 7.0 x 1.8
+85
kΩ
kΩ
kHz
°C
mm
T
OP
See Standard Frequencies and Ordering Information (Pg 8).
Parameters are tested with production test circuit (Pg 3).
Parameters are tested at ambient temperature with test limits guard-banded for specified operating temperature.
Measured as the maximum deviation from the best straight-line fit, per MIL-0-55310.
The Vc Model is described below (Fig 1).
Parameters are described with waveform diagram below (Fig 2).
Not tested in production, guaranteed by design, verified at qualification.
For Frequencies > 600 MHz, Jitter is Integrated across 50 kHz to 80 MHz.
For Frequencies < 600 MHz, Jitter is Integrated across 12 kHz to 20 MHz. (Both per GR-253-CORE Issue3).
9]
Tested with Vc = 0.3V to 3.0V.
Fig 1: V
C
Model - F1 or F2 Enabled
Fig 2: 10K LV PECL Waveform
LV-PECL
Page2 of 9
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev: 06Aug2011
VS-709 Dual Frequency VCSO
Absolute Maximum Ratings
Parameter
Power Supply
Input Current
Output Current
Voltage Control Range
Output Select
Storage Temperature
Soldering Temperature / Duration
Symbol
V
CC
I
IN
I
OUT
V
C
OSelect
T
STR
T
PEAK
/ t
P
Ratings
0 to 6
100
25
0 to V
CC
0 to V
CC
-55 to 125
260 / 40
Unit
V
mA
mA
V
V
°C
°C / sec
Stresses in excess of the absolute maximum ratings can permanently damage the device. Also, exposure to these absolute
maximum ratings for extended periods may adversely affect device reliability. Functional operation is not implied at these or any
other conditions in excess of those represented in the operational sections of this datasheet. Permanent damage is also possible if
any device input (Vc or OS) draws >100 mA.
Test Circuits & Output Load Configuration
Functional Test:
Allows use of standard power supply biasing con-
figuration. Pull down resistors are used for LV-PECL outputs and are
removed for LVDS outputs. Since the LVDS outputs are AC coupled,
the output DC levels cannots be measured.
Production Test:
DC levels shown for VEE, OSelect, & Vc are for
devices configured for 3.3V operation. LV-PECL outputs are DC
coupled to 50Ω test equipment. LVDS outputs are connected to a
digital volt meter, then AC coupled to the test equipment. The digital
volt meter allows for Mid Level & Swing measurements.
LV-PECL to LV-PECL:
For short transmission lengths,
the pull down resistor values shown provide reasonable power con-
sumption and waveform performance.
LVDS to LVDS:
The 100Ω resistor should be removed if this load is
provided internally within the LVDS receiver.
Page3 of 9
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev: 06Aug2011
VS-709 Dual Frequency VCSO
Typical Characteristics: Vc Pull, Vc Pull Linearity, Vc Pull Slope
Page4 of 9
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev: 06Aug2011
VS-709 Dual Frequency VCSO
Typical Characteristics: Phase Noise & Jitter
Page5 of 9
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev: 06Aug2011
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
