74HC273; 74HCT273
Octal D-type flip-flop with reset; positive-edge trigger
Rev. 03 — 24 January 2006
Product data sheet
1. General description
The 74HC273; 74HCT273 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL).
The 74HC273; 74HCT273 has eight edge-triggered, D-type flip-flops with individual
D inputs and Q outputs. The common clock (pin CP) and master reset (pin MR) inputs
load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up
time before the LOW-to-HIGH clock transition, is transferred to the corresponding output
(Qn) of the flip-flop.
All outputs will be forced LOW independently of clock or data inputs by a LOW voltage
level on the MR input.
The device is useful for applications where the true output only is required and the clock
and master reset are common to all storage elements.
2. Features
s
s
s
s
s
Ideal buffer for MOS microprocessor or memory
Common clock and master reset
Eight positive edge-triggered D-type flip-flops
Complies with JEDEC standard no. 7A
ESD protection:
x
HBM EIA/JESD22-A114-C exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V
s
Multiple package options
s
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns.
Symbol Parameter
74HC273
t
PHL
,
t
PLH
t
PHL
f
max
propagation delay CP to Qn
HIGH-to-LOW propagation
delay MR to Qn
maximum input clock
frequency
V
CC
= 5 V; C
L
= 15 pF
V
CC
= 5 V; C
L
= 15 pF
V
CC
= 5 V; C
L
= 15 pF
-
-
-
15
15
66
-
-
-
ns
ns
MHz
Conditions
Min
Typ
Max
Unit
Philips Semiconductors
74HC273; 74HCT273
Octal D-type flip-flop with reset; positive-edge trigger
Table 1:
Quick reference data
…continued
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns.
Symbol Parameter
C
i
C
PD
input capacitance
power dissipation
capacitance
propagation delay CP to Qn
HIGH-to-LOW propagation
delay MR to Qn
maximum input clock
frequency
input capacitance
power dissipation
capacitance
per flip-flop; V
I
= GND
to (V
CC
−
1.5 V)
[1]
Conditions
per flip-flop; V
I
= GND
to V
CC
V
CC
= 5 V; C
L
= 15 pF
V
CC
= 5 V; C
L
= 15 pF
V
CC
= 5 V; C
L
= 15 pF
[1]
Min
-
-
Typ
3.5
20
Max
-
-
Unit
pF
pF
74HCT273
t
PHL
,
t
PLH
t
PHL
f
max
C
i
C
PD
-
-
-
-
-
15
20
36
3.5
23
-
-
-
-
-
ns
ns
MHz
pF
pF
[1]
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
∑(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
∑(C
L
×
V
CC2
×
f
o
) = sum of outputs.
4. Ordering information
Table 2:
Ordering information
Package
Temperature range Name
74HC273
74HC273N
74HC273D
74HC273DB
74HC273PW
74HC273BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
DIP20
SO20
SSOP20
TSSOP20
plastic dual in-line package; 20 leads (300 mil)
plastic shrink small outline package; 20 leads; body width
5.3 mm
plastic thin shrink small outline package; 20 leads; body
width 4.4 mm
SOT146-1
SOT339-1
SOT360-1
SOT764-1
plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
Description
Version
Type number
DHVQFN20 plastic dual in-line compatible thermal enhanced very thin
quad flat package; no leads; 20 terminals;
body 2.5
×
4.5
×
0.85 mm
DIP20
SO20
plastic dual in-line package; 20 leads (300 mil)
74HCT273
74HCT273N
74HCT273D
−40 °C
to +125
°C
−40 °C
to +125
°C
SOT146-1
plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
2 of 26
Philips Semiconductors
74HC273; 74HCT273
Octal D-type flip-flop with reset; positive-edge trigger
Table 2:
Ordering information
…continued
Package
Temperature range Name
Description
plastic shrink small outline package; 20 leads; body width
5.3 mm
plastic thin shrink small outline package; 20 leads; body
width 4.4 mm
Version
SOT339-1
SOT360-1
SOT764-1
SSOP20
TSSOP20
Type number
74HCT273DB
−40 °C
to +125
°C
74HCT273PW
−40 °C
to +125
°C
74HCT273BQ
−40 °C
to +125
°C
DHVQFN20 plastic dual in-line compatible thermal enhanced very thin
quad flat package; no leads; 20 terminals;
body 2.5
×
4.5
×
0.85 mm
5. Functional diagram
3
4
7
8
13
14
17
18
1
11
D0
D1
D2
D3
D4
D5
D6
D7
MR
CP
FF1
TO
FF8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
001aae055
Fig 1. Functional diagram
CP
MR
11
3
4
7
8
13
14
17
18
CP
D0
D1
D2
D3
D4
D5
D6
D7
MR
1
mna763
11
1
C1
R
D0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
D1
D2
D3
D4
D5
D6
D7
3
4
7
8
13
14
17
18
1D
2
5
6
9
12
15
16
19
mna764
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Fig 2. Logic symbol
Fig 3. IEC logic symbol
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
3 of 26
Philips Semiconductors
74HC273; 74HCT273
Octal D-type flip-flop with reset; positive-edge trigger
D0
D1
D2
D3
D
Q
D
Q
D
Q
D
Q
CP
FF1
R
D
CP
CP
FF2
R
D
CP
FF3
R
D
CP
FF4
R
D
MR
Q0
D4
D5
Q1
D6
Q2
D7
Q3
D
Q
D
Q
D
Q
D
Q
CP
FF5
R
D
CP
FF6
R
D
CP
FF7
R
D
CP
FF8
R
D
Q4
Q5
Q6
Q7
001aae056
Fig 4. Logic diagram
74HC_HCT273_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
4 of 26
Philips Semiconductors
74HC273; 74HCT273
Octal D-type flip-flop with reset; positive-edge trigger
6. Pinning information
6.1 Pinning
74HC273
74HCT273
terminal 1
index area
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
GND
(1)
13 D4
12 Q4
GND 10
CP 11
MR
2
3
4
5
6
7
8
9
1
Q0
D0
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
001aae053
74HC273
74HCT273
D1
Q1
Q2
D2
D3
Q3
GND 10
001aae054
Transparent top view
(1) The die substrate is attached to this
pad using conductive die attach
material. It can not be used as supply
pin or output.
Fig 5. Pin configuration DIP20, SO20,
SSOP20 and TSSOP20
Fig 6. Pin configuration DHVQFN20
6.2 Pin description
Table 3:
Symbol
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
CP
Q4
D4
D5
74HC_HCT273_3
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
master reset input (active LOW)
flip-flop output 0
data input 0
data input 1
flip-flop output 1
flip-flop output 2
data input 2
data input 3
flip-flop output 3
ground (0 V)
clock input (LOW-to-HIGH, edge-triggered)
flip-flop output 4
data input 4
data input 5
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 24 January 2006
5 of 26
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