Data Sheet, Rev. 1.3, Jan. 2006
Cover Page
HYS72T128001HR–5–A
HYS72T256000HR–[3.7/5]–A
240-Pin Registered DDR SDRAM Modules
RDIMM
DDR2 SDRAM
RoHS Compliant
Memory Products
Edition 2005-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
©
Infineon Technologies AG 2006.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
HYS72T128001HR–5–A, HYS72T256000HR–[3.7/5]–A
Revision History: 2005-01, Rev. 1.3
Page
Subjects (major changes since last revision)
Added HYS72T128001HR-5-A: Updated Ordering Information, Block Diagrams,
I
DD
Currents, SPD
Codes and Package Outlines accordingly
Added High Temperature Self refresh to Feature List,
Operating Temperature and to SPD Codes
20
29
28, 32
35
Changed footnote 1 (Table 9) into “Attention”
Added footnote 2 to IDD Currents (Table 18)
SPD Codes updated
Package Outline figure updated
Previous Version: 2005-08, Rev. 1.2
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send us your proposal (including a reference to this document) to:
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Template: mp_a4_s_rev321 / 3 / 2005-10-05
HYS72T[128/256]00xHR–[3.7/5]–A
Registered DDR2 SDRAM Modules
Table of Contents
1
1.1
1.2
2
2.1
2.2
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.4
3.4.1
3.4.2
4
5
6
Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration and Block Diagrams
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speed Grades Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Currents Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Currents Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
20
20
21
21
22
26
27
30
30
SPD Codes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Package Outlines
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Data Sheet
4
Rev. 1.3, 2005-01
02182004-ZZS1-BO6E
240-Pin Registered DDR SDRAM Modules
RDIMM
HYS72T128001HR–5–A
HYS72T256000HR–[3.7/5]–A
1
Overview
This chapter gives an overview of the 240-Pin Registered DDR SDRAM Modules product family and describes
its main characteristics.
1.1
•
Features
•
•
•
•
•
•
•
•
•
Auto Refresh (CBR) and Self Refresh
Average Refresh Period 7.8 µs at a
T
CASE
lower
than 85 °C, 3.9 µs between 85 °C and 95 °C
Programmable self refresh rate via EMRS2 setting
All inputs and outputs SSTL_18 compatible
Off-Chip Driver Impedance Adjustment (OCD) and
On-Die Termination (ODT)
Serial Presence Detect with E
2
PROM
RDIMM Dimensions (nominal):
30,00 mm high, 133.35 mm wide
Based on JEDEC standard reference card layouts
Raw Card “A-F” and “C-H”
RoHS compliant products
1)
•
•
•
•
•
240-Pin PC2–4200 and PC2–3200 DDR2 SDRAM
memory modules for PC, Workstation and Server
main memory applications.
One rank 128M x 72, 256M x 72 module
organization and 128M x 8, 256M
×4
chip
organization
Standard Double-Data-Rate-Two Synchronous
DRAMs (DDR2 SDRAM) with a single + 1.8 V
(± 0.1 V) power supply
1 and 2 GByte module built with 1 Gbit DDR2
SDRAMs in P-TFBGA-68 chipsize packages.
All speed grades faster than DDR2-400 comply with
DDR2-400 timing specifications as well.
Programmable CAS Latencies (3, 4 & 5), Burst
Length (4 & 8) and Burst Type
Performance for PC2–4200–444
Table 1
Product Type Speed Code
Speed Grade
max. Clock Frequency
@CL5
@CL4
@CL3
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
–3.7
PC2–4200 4–4–4
Unit
—
MHz
MHz
MHz
ns
ns
ns
ns
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
266
266
200
15
15
45
60
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic
equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January
2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and
polybrominated biphenyl ethers.
Data Sheet
5
Rev. 1.3, 2005-01
02182004-ZZS1-BO6E
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