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HY5V56FF-HI: 产品描述Synchronous DRAM, 16MX16, 5.4ns, CMOS, PBGA54, 8 X 10 MM, 0.80 MM PITCH, FBGA-54; 产品类别存储存储; 文件大小575KB，共47页; 制造商SK Hynix(海力士); 官网地址http://www.hynix.com/eng/

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HY5V56FF-HI概述

Synchronous DRAM, 16MX16, 5.4ns, CMOS, PBGA54, 8 X 10 MM, 0.80 MM PITCH, FBGA-54

HY5V56FF-HI规格参数

参数名称	属性值
是否Rohs认证	不符合
厂商名称	SK Hynix(海力士)
零件包装代码	BGA
包装说明	TFBGA, BGA54,9X9,32
针数	54
Reach Compliance Code	compliant
ECCN代码	EAR99
访问模式	FOUR BANK PAGE BURST
最长访问时间	5.4 ns
其他特性	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	133 MHz
I/O 类型	COMMON
交错的突发长度	1,2,4,8
JESD-30 代码	R-PBGA-B54
长度	10 mm
内存密度	268435456 bit
内存集成电路类型	SYNCHRONOUS DRAM
内存宽度	16
功能数量	1
端口数量	1
端子数量	54
字数	16777216 words
字数代码	16000000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-40 °C
组织	16MX16
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	TFBGA
封装等效代码	BGA54,9X9,32
封装形状	RECTANGULAR
封装形式	GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）	NOT SPECIFIED
电源	3.3 V
认证状态	Not Qualified
刷新周期	8192
座面最大高度	1.1 mm
自我刷新	YES
连续突发长度	1,2,4,8,FP
最大待机电流	0.003 A
最大压摆率	0.09 mA
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	3 V
标称供电电压 (Vsup)	3.3 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子形式	BALL
端子节距	0.8 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	8 mm

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256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O

256M (16Mx16bit) Hynix SDRAM

Memory

Memory Cell Array

- Organized as 4banks of 4,194,304 x 16

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev 1.1 / Dec. 2007

Synchronous DRAM Memory 256Mbit

HY5V56F(L)F(P)-xI Series

DESCRIPTION

The Hynix Synchronous DRAM is suited for advaced-consumer application which use the batteries such as Image dis-

player application (Digital still camera etc.) and portable applications (portable multimedia player and portable audio

player). Also, Hynix SDRAMs is used high-speed consumer applications. Short for Hynix Synchronous DRAM, a type of

DRAM that can run at much higher clock speeds memory.

The Hynix HY5V56F(L)F(P)-xI Synchronous DRAM is 268,435,456bit CMOS Synchronous DRAM, ideally suited for the

consumer memory applications which requires large memory density and high bandwidth. It is organized as 4banks of

4,194,304 x 16 I/O.

Synchronous DRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Synchronous

DRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization

with the input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x16

Input/ Output bus. All the commands are latched in synchronization with the rising edge of CLK.

The Synchronous DRAM provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4,

8 locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is

initiated at the end of the burst access. The Synchronous DRAM uses an internal pipelined architecture to achieve

high-speed operation. This architecture is compartible with the 2n rule of prefetch architectures, but it also allows the

column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one

bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed,

randon-access operation.

Read and write accesses to the Hynix Synchronous DRAM are burst oriented;

accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.

Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.

The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be

accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and

the starting column location for the burst access.

All inputs are LVTTL compatible. Devices will have a V

and V

DDQ

supply of 3.3V (nominal).

Rev 1.1 / Dec. 2007

HY5V56FF-HI相似产品对比

	HY5V56FF-HI	HY5V56FLF-HI	HY5V56FLF-6I	HY5V56FLFP-6I	HY5V56FF-6I	HY5V56FFP-HI	HY5V56FLFP-HI	HY5V56FFP-6I
描述	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PBGA54, 8 X 10 MM, 0.80 MM PITCH, FBGA-54	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PBGA54, 8 X 10 MM, 0.80 MM PITCH, FBGA-54	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PBGA54, 8 X 10 MM, 0.80 MM PITCH, FBGA-54	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PBGA54, 8 X 10 MM, 0.80 MM PITCH, LEAD FREE, FBGA-54	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PBGA54, 8 X 10 MM, 0.80 MM PITCH, FBGA-54	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PBGA54, 8 X 10 MM, 0.80 MM PITCH, LEAD FREE, FBGA-54	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PBGA54, 8 X 10 MM, 0.80 MM PITCH, LEAD FREE, FBGA-54	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PBGA54, 8 X 10 MM, 0.80 MM PITCH, LEAD FREE, FBGA-54
是否Rohs认证	不符合	不符合	不符合	符合	不符合	符合	符合	符合
厂商名称	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)
零件包装代码	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
包装说明	TFBGA, BGA54,9X9,32	TFBGA, BGA54,9X9,32	TFBGA, BGA54,9X9,32	TFBGA, BGA54,9X9,32	TFBGA, BGA54,9X9,32	TFBGA, BGA54,9X9,32	TFBGA, BGA54,9X9,32	TFBGA, BGA54,9X9,32
针数	54	54	54	54	54	54	54	54
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	unknown	compliant	unknown
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
最长访问时间	5.4 ns	5.4 ns	5.4 ns	5.4 ns	5.4 ns	5.4 ns	5.4 ns	5.4 ns
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	133 MHz	133 MHz	166 MHz	166 MHz	166 MHz	133 MHz	133 MHz	166 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
交错的突发长度	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8
JESD-30 代码	R-PBGA-B54	R-PBGA-B54	R-PBGA-B54	R-PBGA-B54	R-PBGA-B54	R-PBGA-B54	R-PBGA-B54	R-PBGA-B54
长度	10 mm	10 mm	10 mm	10 mm	10 mm	10 mm	10 mm	10 mm
内存密度	268435456 bit	268435456 bit	268435456 bit	268435456 bit	268435456 bit	268435456 bit	268435456 bit	268435456 bit
内存集成电路类型	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
内存宽度	16	16	16	16	16	16	16	16
功能数量	1	1	1	1	1	1	1	1
端口数量	1	1	1	1	1	1	1	1
端子数量	54	54	54	54	54	54	54	54
字数	16777216 words	16777216 words	16777216 words	16777216 words	16777216 words	16777216 words	16777216 words	16777216 words
字数代码	16000000	16000000	16000000	16000000	16000000	16000000	16000000	16000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
组织	16MX16	16MX16	16MX16	16MX16	16MX16	16MX16	16MX16	16MX16
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA
封装等效代码	BGA54,9X9,32	BGA54,9X9,32	BGA54,9X9,32	BGA54,9X9,32	BGA54,9X9,32	BGA54,9X9,32	BGA54,9X9,32	BGA54,9X9,32
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	260	NOT SPECIFIED	260	260	260
电源	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
刷新周期	8192	8192	8192	8192	8192	8192	8192	8192
座面最大高度	1.1 mm	1.1 mm	1.1 mm	1.1 mm	1.1 mm	1.1 mm	1.1 mm	1.1 mm
自我刷新	YES	YES	YES	YES	YES	YES	YES	YES
连续突发长度	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP
最大待机电流	0.003 A	0.003 A	0.003 A	0.003 A	0.003 A	0.003 A	0.003 A	0.003 A
最大压摆率	0.09 mA	0.09 mA	0.1 mA	0.1 mA	0.1 mA	0.09 mA	0.09 mA	0.1 mA
最大供电电压 (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子形式	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
端子节距	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	20	NOT SPECIFIED	20	20	20
宽度	8 mm	8 mm	8 mm	8 mm	8 mm	8 mm	8 mm	8 mm

HY5V56FF-HI

HY5V56FF-HI概述

HY5V56FF-HI规格参数

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HY5V56FF-HI相似产品对比

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