TMS27C512 65536 BY 8 BIT UV ERASABLE
TMS27PC512 65536 BY 8 BIT
PROGRAMMABLE READ ONLY MEMORIES
SMLS512G − NOVEMBER 1985 − REVISED SEPTEMBER 1997
D
Organization . . . 65 536 by 8 Bits
D
Single 5-V Power Supply
D
Pin Compatible With Existing 512K MOS
D
D
ROMs, PROMs, and EPROMs
All Inputs/Outputs Fully TTL Compatible
Max Access/Min Cycle Time
V
CC
±
10%
’27C/PC512-10
100 ns
’27C/PC512-12
120 ns
’27C/PC512-15
150 ns
’27C/PC512-20
200 ns
’27C/PC512-25
250 ns
Power Saving CMOS Technology
Very High-Speed SNAP! Pulse
Programming
3-State Output Buffers
400-mV Minimum DC Noise Immunity With
Standard TTL Loads
Latchup Immunity of 250 mA on All Input
and Output Lines
Low Power Dissipation ( V
CC
= 5.25 V )
− Active . . . 158 mW Worst Case
− Standby . . . 1.4 mW Worst Case
(CMOS Input Levels)
Temperature Range Options
512K EPROM Available With MIL-STD-883C
Class B High Reliability Processing
(SMJ27C512)
J PACKAGE
( TOP VIEW )
D
D
D
D
D
D
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A14
A13
A8
A9
A11
G / V
PP
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
FM PACKAGE
( TOP VIEW )
A7
A12
A15
NU
VCC
A14
A13
4
3 2 1 32 31 30
29
28
27
26
25
24
23
22
21
14 15 16 17 18 19 20
D
D
description
The TMS27C512 series are 65 536 by 8-bit
(524 288-bit), ultraviolet (UV) light erasable,
electrically programmable read-only memories
(EPROMs).
The TMS27PC512 series are 65 536 by 8-bit
(524 288-bit), one-time programmable (OTP)
electrically programmable read-only memories
(PROMs).
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
5
6
7
8
9
10
11
12
13
A8
A9
A11
NC
G / V
PP
A10
E
DQ7
DQ6
PIN NOMENCLATURE
A0 −A15
E
DQ0 −DQ7
G / VPP
GND
NC
NU
VCC
Address Inputs
Chip Enable/Power Down
Inputs (programming) / Outputs
13-V Programming Power Supply
Ground
No Internal Connection
Make No External Connection
5-V Power Supply
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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DQ1
DQ2
GND
NU
DQ3
DQ4
DQ5
Copyright
1997, Texas Instruments Incorporated
1
SMLS512G − NOVEMBER 1985 − REVISED SEPTEMBER 1997
TMS27C512 65536 BY 8 BIT UV ERASABLE
TMS27PC512 65536 BY 8 BIT
PROGRAMMABLE READ ONLY MEMORIES
description (continued)
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pullup resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The data outputs are 3-state for connecting multiple devices to a common bus. The TMS27C512 and the
TMS27PC512 are pin compatible with 28-pin 512K MOS ROMs, PROMs, and EPROMs.
The TMS27C512 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27PC512 OTP PROM is supplied in a 32-lead
plastic leaded chip carrier package using 1,25-mm (50-mil) lead spacing (FM suffix).
The TMS27C512 and TMS27PC512 are offered with two choices of temperature ranges of 0°C to 70°C (JL and
FML suffix) and − 40°C to 85°C (JE and FME suffix). See Table 1.
All package styles conform to JEDEC standards.
Table 1. Temperature Range Suffixes
EPROM
AND
OTP PROM
TMS27C512-xxx
TMS27PC512-xxx
SUFFIX FOR OPERATING
FREE-AIR TEMPERATURE RANGES
0°C TO 70°C
JL
FML
− 40°C TO 85°C
JE
FME
These EPROMs and OTP PROMs operate from a single 5-V supply (in the read mode), thus are ideal for use
in microprocessor-based systems. One other 13-V supply is needed for programming. All programming signals
are TTL level. The device is programmed using the SNAP! Pulse programming algorithm. The SNAP! Pulse
programming algorithm uses a V
PP
of 13 V and a V
CC
of 6.5 V for a nominal programming time of seven seconds.
For programming outside the system, existing EPROM programmers can be used. Locations can be
programmed singly, in blocks, or at random.
2
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TMS27C512 65536 BY 8 BIT UV ERASABLE
TMS27PC512 65536 BY 8 BIT
PROGRAMMABLE READ ONLY MEMORIES
SMLS512G − NOVEMBER 1985 − REVISED SEPTEMBER 1997
operation
The seven modes of operation are listed in Table 2. The read mode requires a single 5-V supply. All inputs are
TTL level except for V
PP
during programming (13 V for SNAP! Pulse) and 12 V on A9 for signature mode.
Table 2. Operation Modes
MODE†
FUNCTION
E
G / VPP
VCC
A9
A0
DQ0 −DQ7
† X can be VIL or VIH.
‡ VH = 12 V
±
0.5 V.
READ
VIL
VIL
VCC
X
X
Data Out
OUTPUT
DISABLE
VIL
VIH
VCC
X
X
Hi-Z
STANDBY
VIH
X
VCC
X
X
Hi-Z
PROGRAMMING
VIL
VPP
VCC
X
X
Data In
VERIFY
VIL
VIL
VCC
X
X
Data Out
PROGRAM
INHIBIT
VIH
VPP
VCC
X
X
Hi-Z
VH‡
VIL
CODE
MFG
97
DEVICE
85
SIGNATURE
MODE
VIL
VIL
VCC
VH‡
VIH
read/ output disable
When the outputs of two or more TMS27C512s or TMS27PC512s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the competing outputs
of the other devices. To read the output of a single device, a low-level signal is applied to the E and G/ V
PP
pins.
All other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these
pins. Output data is accessed at pins DQ0 through DQ7.
latchup immunity
Latchup immunity on the TMS27C512 and TMS27PC512 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices
are interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup
without compromising performance or packing density.
power down
Active I
CC
supply current can be reduced from 30 mA to 500
µA
( TTL-level inputs) or 250
µA
(CMOS-level
inputs) by applying a high TTL / CMOS signal to the E pin. In this mode all outputs are in the high-impedance
state.
erasure ( TMS27C512)
Before programming, the TMS27C512 EPROM is erased by exposing the chip through the transparent lid
to a high intensity ultraviolet light (wavelength 2537 angstroms). EPROM erasure before programming is
necessary to assure that all bits are in the logic high state. Logic lows are programmed into the desired locations.
A programmed logic low can be erased only by ultraviolet light. The recommended minimum exposure dose
(UV intensity
×
exposure time) is 15-W⋅s / cm
2
. A typical 12-mW / cm
2
, filterless UV lamp erases the device in
21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. It should be noted that
normal ambient light contains the correct wavelength for erasure. Therefore, when using the TMS27C512, the
window should be covered with an opaque label.
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3
SMLS512G − NOVEMBER 1985 − REVISED SEPTEMBER 1997
TMS27C512 65536 BY 8 BIT UV ERASABLE
TMS27PC512 65536 BY 8 BIT
PROGRAMMABLE READ ONLY MEMORIES
initializing (TMS27PC512)
The one-time programmable TMS27PC512 PROM is provided with all bits in the logic high state, then logic lows
are programmed into the desired locations. Logic lows programmed into a PROM cannot be erased.
SNAP! Pulse programming
The 512K EPROM and OTP PROM are programmed using the TI SNAP! Pulse programming algorithm
illustrated by the flowchart in Figure 1, which programs in a nominal time of seven seconds. Actual programming
time varies as a function of the programmer used.
The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (µs) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-µs
pulses per byte are provided before a failure is recognized.
The programming mode is achieved with G/ V
PP
= 13 V, V
CC
= 6.5 V, and E = V
IL
. Data is presented in parallel
(eight bits) on pins DQ0 to DQ7. Once addresses and data are stable, E is pulsed.
More than one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with
V
CC
= 5 V, G / V
PP
= V
IL,
and E = V
IL
.
program inhibit
Programming can be inhibited by maintaining a high level input on the E pin.
program verify
Programmed bits can be verified when G / V
PP
and E = V
IL
.
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 is forced to 12 V. Two identifier bytes are accessed by toggling A0. All other addresses must
be held low. the signature code for these devices is 9785. A0 selects the manufacturer’s code 97 (Hex), and
A0 high selects the device code 85, as shown in Table 3.
Table 3. Signature Mode
IDENTIFIER†
Manufacturer Code
Device Code
PINS
A0
VIL
VIH
DQ7
1
1
DQ6
0
0
DQ5
0
0
DQ4
1
0
DQ3
0
0
DQ2
1
1
DQ1
1
0
DQ0
1
1
HEX
97
85
† E = G = VIL, A9 = VH, A1 −A8 = VIL, A10 −A15 = VIL, PGM = VIH or VIL.
4
POST OFFICE BOX 1443
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HOUSTON, TEXAS 77251−1443
TMS27C512 65536 BY 8 BIT UV ERASABLE
TMS27PC512 65536 BY 8 BIT
PROGRAMMABLE READ ONLY MEMORIES
SMLS512G − NOVEMBER 1985 − REVISED SEPTEMBER 1997
Start
Address = First Location
VCC = 6.5 V
±
0.25 V, G / VPP = 13 V
±
0.25 V
Program One Pulse = tw = 100
µs
Increment Address
Program
Mode
Last
Address
?
Yes
No
Address = First Location
X=0
Program One Pulse = tw = 100
µs
No
Increment
Address
Verify
One Byte
Fail
X=X+1
X = 10?
Interactive
Mode
Pass
No
Last
Address
?
Yes
Yes
Device Failed
VCC = 5 V
±
0.5 V, G / VPP = VIL
Compare
All Bytes
To Original
Data
Pass
Device Passed
Fail
Final
Verification
Figure 1. SNAP! Pulse Programming Flow Chart
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5
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