74HC4060-Q100; 74HCT4060-Q100
14-stage binary ripple counter with oscillator
Rev. 1 — 2 August 2012
Product data sheet
1. General description
The 74HC4060-Q100; 74HCT4060-Q100 are high-speed Si-gate CMOS devices that
comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky
TTL (LSTTL).
The 74HC4060-Q100; 74HCT4060-Q100 are 14-stage ripple-carry counter/dividers and
oscillators with three oscillator terminals (RS, RTC and CTC), ten buffered outputs (Q3 to
Q9 and Q11 to Q13) and an overriding asynchronous master reset (MR). The oscillator
configuration allows design of either RC or crystal oscillator circuits. The oscillator may be
replaced by an external clock signal at input RS. In this case keep the other oscillator pins
(RTC and CTC) floating. The counter advances on the negative-going transition of RS. A
HIGH level on MR resets the counter (Q3 to Q9 and Q11 to Q13 = LOW), independent of
other input conditions. In the HCT version, the MR input is TTL compatible, but the RS
input has CMOS input switching levels and can be driven by a TTL output by using a
pull-up resistor to V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
All active components on chip
RC or crystal oscillator configuration
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
3. Applications
Control counters
Timers
Frequency dividers
Time-delay circuits
NXP Semiconductors
74HC4060-Q100; 74HCT4060-Q100
14-stage binary ripple counter with oscillator
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC4060D-Q100
74HCT4060D-Q100
74HC4060PW-Q100
74HC4060BQ-Q100
74HCT4060BQ-Q100
40 C
to +125
C
40 C
to +125
C
TSSOP16
40 C
to +125
C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
Version
SOT109-1
Type number
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
DHVQFN16 plastic dual in-line compatible thermal-enhanced
SOT763-1
very thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
5. Functional diagram
10
9
RTC CTC
11
12
RS
MR
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q11
Q12
Q13
7
5
4
6
14
13
15
1
2
3
001aai467
Fig 1.
Logic symbol
CTR14
!G
9
10
11
12
CT = 0
CX
RX
RCX
CT
9
11
13
(a)
+
3
7
5
4
6
14
13
15
1
2
3
11
12
CTR14
3
7
5
4
AND
+
CT
CT = 0
9
11
13
(b)
001aai468
6
14
13
15
1
2
3
Fig 2.
IEC logic symbol
74HC_HCT4060_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 August 2012
2 of 24
NXP Semiconductors
74HC4060-Q100; 74HCT4060-Q100
14-stage binary ripple counter with oscillator
10
RTC
11
RS
9
CTC
CP
MR
14-STAGE BINARY COUNTER
Q4
5
4
Q5
6
Q6
Q7
14
Q8
13
Q9
15
1
Q11 Q12 Q13
2
3
001aai113
12
MR
Q3
7
Fig 3.
Functional diagram
CTC
RTC
RS
FF
1
CP
Q
MR
MR
FF
4
CP
Q
MR
FF
10
CP
Q
MR
FF
12
CP
Q
MR
FF
14
CP
Q
MR
Q3
Q9
Q11
Q13
001aai114
Fig 4.
Logic diagram
74HC_HCT4060_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 August 2012
3 of 24
NXP Semiconductors
74HC4060-Q100; 74HCT4060-Q100
14-stage binary ripple counter with oscillator
6. Pinning information
6.1 Pinning
+&4
+&74
4
4
4
4
4
4
4
*1'
DDD
+&4
+&74
WHUPLQDO
LQGH[ DUHD
4
4
4
4
4
4
*1'
&7&
9
9
&&
4
4
4
05
56
57&
DDD
9
&&
4
4
4
05
56
57&
&7&
7UDQVSDUHQW WRS YLHZ
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as
supply pin or input.
Fig 5.
Pin configuration SO16 and TSSOP16
Fig 6.
Pin configuration DHVQFN16
6.2 Pin description
Table 2.
Symbol
Q11 to Q13
Q3 to Q9
GND
CTC
RTC
RS
MR
V
CC
Pin description
Pin
1, 2, 3
7, 5, 4, 6, 14, 13, 15
8
9
10
11
12
16
Description
counter output
counter output
ground (0 V)
external capacitor connection
external resistor connection
clock input /oscillator pin
master reset input (active HIGH)
supply voltage
74HC_HCT4060_Q100
All information provided in this document is subject to legal disclaimers.
4
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 August 2012
4 of 24
NXP Semiconductors
74HC4060-Q100; 74HCT4060-Q100
14-stage binary ripple counter with oscillator
7. Functional description
1
RS
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192 16384
MR
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q11
Q12
Q13
001aai117
Fig 7.
Timing diagram
8. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
[1]
[1]
Conditions
Min
0.5
-
-
-
-
50
65
Max
+7
20
20
25
50
-
+150
Unit
V
mA
mA
mA
mA
mA
C
74HC_HCT4060_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 August 2012
5 of 24
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