74HC00; 74HCT00
Quad 2-input NAND gate
Rev. 6 — 14 December 2011
Product data sheet
1. General description
The 74HC00; 74HCT00 are high-speed Si-gate CMOS devices that comply with JEDEC
standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC00; 74HCT00 provides a quad 2-input NAND function.
2. Features and benefits
Input levels:
For 74HC00: CMOS level
For 74HCT00: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC00N
74HCT00N
74HC00D
74HCT00D
74HC00DB
74HCT00DB
74HC00PW
74HCT00PW
74HC00BQ
74HCT00BQ
40 C
to +125
C
DHVQFN14
40 C
to +125
C
TSSOP14
40 C
to +125
C
SSOP14
40 C
to +125
C
SO14
plastic small outline package; 14 leads; body width
3.9 mm
plastic shrink small outline package; 14 leads; body
width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT108-1
SOT337-1
SOT402-1
40 C
to +125
C
Name
DIP14
Description
plastic dual in-line package; 14 leads (300 mil)
Version
SOT27-1
Type number
plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
NXP Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
4. Functional diagram
1
1 1A
2 1B
4 2A
5 2B
9 3A
10 3B
12 4A
13 4B
1Y 3
2
4
2Y 6
5
9
10
12
13
mna212
&
3
&
6
3Y 8
&
8
A
4Y 11
&
mna246
11
B
Y
mna211
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one gate)
5. Pinning information
5.1 Pinning
74HC00
74HCT00
terminal 1
index area
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
8
3A
3Y
1B
1Y
2A
2B
2Y
2
3
4
5
6
7
GND
3Y
8
GND
(1)
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
3A
001aal324
74HC00
74HCT00
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
001aal323
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration DIP14, SO14 and (T)SSOP14
Fig 5.
Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
Description
data input
data input
74HC_HCT00
All information provided in this document is subject to legal disclaimers.
1
1A
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 14 December 2011
2 of 16
NXP Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
Table 2.
Symbol
1Y to 4Y
GND
V
CC
Pin description
…continued
Pin
3, 6, 8, 11
7
14
Description
data output
ground (0 V)
supply voltage
6. Functional description
Table 3.
Input
nA
L
X
H
[1]
Function table
[1]
Output
nB
X
L
H
nY
H
H
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
DIP14 package
SO14, (T)SSOP14 and
DHVQFN14 packages
[1]
[2]
[2]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
[1]
[1]
Min
0.5
-
-
-
-
50
65
-
-
Max
+7
20
20
25
50
-
+150
750
500
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For DIP14 package: P
tot
derates linearly with 12 mW/K above 70
C.
For SO14 package: P
tot
derates linearly with 8 mW/K above 70
C.
For (T)SSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN14 packages: P
tot
derates linearly with 4.5 mW/K above 60
C.
74HC_HCT00
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 14 December 2011
3 of 16
NXP Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
74HC00
Min
2.0
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
74HCT00
Min
4.5
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
C
ns/V
ns/V
ns/V
Unit
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74HC00
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
=
20 A;
V
CC
= 2.0 V
I
O
=
20 A;
V
CC
= 4.5 V
I
O
=
20 A;
V
CC
= 6.0 V
-
-
-
2.0
4.5
6.0
4.32
5.81
0
0
0
0.15
0.16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
1
20
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1
40
V
V
V
V
V
V
V
V
V
V
A
A
-
-
-
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
-
-
-
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
Conditions
Min
25
C
Typ
Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
I
O
=
4.0
mA; V
CC
= 4.5 V -
I
O
=
5.2
mA; V
CC
= 6.0 V -
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A;
V
CC
= 2.0 V
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 6.0 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
input leakage
current
supply current
V
I
= V
CC
or GND;
V
CC
= 6.0 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
-
-
-
-
-
-
-
74HC_HCT00
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 14 December 2011
4 of 16
NXP Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
Table 6.
Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
C
I
74HCT00
V
IH
V
IL
V
OH
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
V
CC
= 4.5 V to 5.5 V
V
CC
= 4.5 V to 5.5 V
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
I
O
=
20 A
I
O
=
4.0
mA
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
I
CC
input leakage
current
supply current
additional
supply current
V
I
= V
CC
or GND;
V
CC
= 6.0 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
-
-
-
-
0
0.15
-
-
150
-
-
-
-
-
-
-
-
-
-
0.1
0.33
1
20
675
-
-
-
-
-
0.1
0.4
1
40
735
V
V
A
A
A
-
-
4.5
4.32
-
-
4.4
3.84
-
-
4.4
3.7
-
-
V
V
-
-
1.6
1.2
-
-
2.0
-
-
0.8
2.0
-
-
0.8
V
V
input
capacitance
Conditions
Min
-
25
C
Typ
3.5
Max
-
-
40 C
to +85
C 40 C
to +125
C
Unit
Min
-
Max
-
Min
-
Max
pF
per input pin;
-
V
I
= V
CC
2.1 V; I
O
= 0 A;
other inputs at V
CC
or GND;
V
CC
= 4.5 V to 5.5 V
-
C
I
input
capacitance
3.5
-
-
-
-
-
pF
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; C
L
= 50 pF; for load circuit see
Figure 7.
Symbol Parameter
Conditions
Min
74HC00
t
pd
propagation delay nA, nB to nY; see
Figure 6
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 5.0 V; C
L
= 15 pF
V
CC
= 6.0 V
t
t
transition time
see
Figure 6
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
[2]
[1]
25
C
Typ
Max
40 C
to +125
C
Unit
Max
(85
C)
Max
(125
C)
-
-
-
-
-
-
-
25
9
7
7
19
7
6
-
-
-
-
-
-
-
115
23
-
20
95
19
16
135
27
-
23
110
22
19
ns
ns
ns
ns
ns
ns
ns
74HC_HCT00
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 14 December 2011
5 of 16
嵌入式系统
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