74HC123-Q100; 74HCT123-Q100
Dual retriggerable monostable multivibrator with reset
Rev. 1 — 1 August 2012
Product data sheet
1. General description
The 74HC123-Q100; 74HCT123-Q100 are high-speed Si-gate CMOS devices and are pin
compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74HC123-Q100; 74HCT123-Q100 are dual retriggerable monostable multivibrators
with output pulse width control by three methods:
1. The basic pulse is defined by the selection of the external resistor (R
EXT
) and
capacitor (C
EXT
).
2. Once triggered, the basic output pulse width may be extended by retriggering the
gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By
repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made
as long as desired. Alternatively an output delay can be terminated at any time by a
LOW-going edge on input nRD, which also inhibits the triggering.
3. An internal connection from nRD to the input gates makes it possible to trigger the
circuit by a HIGH-going signal at input nRD as shown in
Table 3.
Schmitt trigger action in the nA and nB inputs, makes the circuit highly tolerant to slower
input rise and fall times.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
DC triggered from active HIGH or active LOW inputs
Retriggerable for very long pulses up to 100 % duty factor
Direct reset terminates output pulse
Schmitt trigger action on all inputs except for the reset input
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0
)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
NXP Semiconductors
74HC123-Q100; 74HCT123-Q100
Dual retriggerable monostable multivibrator with reset
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC123D-Q100
74HCT123D-Q100
74HC123PW-Q100
74HCT123PW-Q100
74HC123BQ-Q100
40 C
to +125
C
40 C
to +125
C
TSSOP16
40 C
to +125
C
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT403-1
SOT763-1
Type number
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
4. Functional diagram
14
15
S
1A
1
T
2
Q
4
Q
1CEXT
1REXT/CEXT
13
1Q
1Q
1B
RD
3
6
7
S
2CEXT
1RD
2REXT/CEXT
2A
9
T
10
Q
5
2Q
Q
12
2Q
2B
RD
11
001aaa610
2RD
Fig 1.
Functional diagram
74HC_HCT123_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 1 August 2012
2 of 23
NXP Semiconductors
74HC123-Q100; 74HCT123-Q100
Dual retriggerable monostable multivibrator with reset
14
15
1
2
1CEXT 14
2CEXT
6
3
CX
RCX
&
4
R
13
1REXT/CEXT
15
2REXT/CEXT
S
1 1A
9 2A
2 1B
10 2B
3 1RD
11 2RD
T
Q
1Q
4
2Q 12
11
mna515
7
6
CX
RCX
&
12
R
mna516
Q
1Q 13
2Q 5
7
9
10
5
RD
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
nREXT/CEXT
V
CC
nRD
R
CL
R
CL
nQ
nQ
V
CC
V
CC
R
CL
nA
CL
CL
nB
R
mna518
Fig 4.
Logic diagram
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
74HC_HCT123_Q100
Product data sheet
Rev. 1 — 1 August 2012
3 of 23
NXP Semiconductors
74HC123-Q100; 74HCT123-Q100
Dual retriggerable monostable multivibrator with reset
5. Pinning information
5.1 Pinning
+&4
WHUPLQDO
LQGH[ DUHD
%
*1'
$
9
9
&&
5(;7&(;7
&(;7
4
4
5'
%
$
+&4
+&74
$
%
5'
4
4
&(;7
5(;7&(;7
*1'
DDD
9
&&
5(;7&(;7
&(;7
4
4
5'
%
$
5'
4
4
&(;7
5(;7&(;7
DDD
7UDQVSDUHQW WRS YLHZ
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as
supply pin or input.
Fig 5.
Pin configuration for SO16 and TSSOP16
Fig 6.
Pin configuration for DHVQFN16
5.2 Pin description
Table 2.
Symbol
1A
1B
1RD
1Q
2Q
2CEXT
2REXT/CEXT
GND
2A
2B
2RD
2Q
1Q
1CEXT
1REXT/CEXT
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
negative-edge triggered input 1
positive-edge triggered input 1
direct reset LOW and positive-edge triggered input 1
active LOW output 1
active HIGH output 2
external capacitor connection 2
external resistor and capacitor connection 2
ground (0 V)
negative-edge triggered input 2
positive-edge triggered input 2
direct reset LOW and positive-edge triggered input 2
active LOW output 2
active HIGH output 1
external capacitor connection 1
external resistor and capacitor connection 1
supply voltage
74HC_HCT123_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 1 August 2012
4 of 23
NXP Semiconductors
74HC123-Q100; 74HCT123-Q100
Dual retriggerable monostable multivibrator with reset
6. Functional description
Table 3.
Input
nRD
L
X
X
H
H
[1]
Function table
[1]
Output
nA
X
H
X
L
L
nB
X
X
L
H
H
nQ
L
L
[2]
L
[2]
nQ
H
H
[2]
H
[2]
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= LOW-to-HIGH transition;
= HIGH-to-LOW transition;
= one HIGH level output pulse;
= one LOW level output pulse.
[2]
If the monostable was triggered before this condition was established, the pulse continues as programmed.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
SO16 package
TSSOP16 package
DHVQFN16 package
[3]
[4]
[5]
For SO16 packages: P
tot
derates linearly with 8 mW/K above 70
C.
For TSSOP16 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN16 packages: P
tot
derates linearly with 4.5 mW/K above 60
C.
[3]
[4]
[5]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
except for pins nREXT/CEXT;
V
O
=
0.5
V to (V
CC
+ 0.5 V)
Min
0.5
-
-
-
-
-
65
-
-
-
Max
+7
20
20
25
50
50
+150
500
500
500
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
mW
74HC_HCT123_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 1 August 2012
5 of 23
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