74HC00-Q100; 74HCT00-Q100
Quad 2-input NAND gate
Rev. 1 — 12 July 2012
Product data sheet
1. General description
The 74HC00-Q100; 74HCT00-Q100 are high-speed Si-gate CMOS devices that comply
with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL
(LSTTL).
The 74HC00-Q100; 74HCT00-Q100 provides a quad 2-input NAND function.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Input levels:
For 74HC00-Q100: CMOS level
For 74HCT00-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0
)
Multiple package options
NXP Semiconductors
74HC00-Q100; 74HCT00-Q100
Quad 2-input NAND gate
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC00D-Q100
74HCT00D-Q100
74HC00PW-Q100
74HCT00PW-Q100
74HC00BQ-Q100
74HCT00BQ-Q100
40 C
to +125
C
40 C
to +125
C
TSSOP14
40 C
to +125
C
SO14
Description
plastic small outline package; 14 leads; body width
3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
4. Functional diagram
1
1 1A
2 1B
4 2A
5 2B
9 3A
10 3B
12 4A
13 4B
1Y 3
2
4
2Y 6
5
9
10
12
13
mna212
&
3
&
6
3Y 8
&
8
A
4Y 11
&
mna246
11
B
Y
mna211
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one gate)
74HC_HCT00_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 12 July 2012
2 of 15
NXP Semiconductors
74HC00-Q100; 74HCT00-Q100
Quad 2-input NAND gate
5. Pinning information
5.1 Pinning
74HC00-Q100
74HCT00-Q100
terminal 1
index area
1B
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
8
3A
3Y
1Y
2A
2B
2Y
2
3
4
5
6
7
GND
3Y
8
GND
(1)
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
3A
aaa-003148
74HC00-Q100
74HCT00-Q100
aaa-003147
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration SO14 and TSSOP14
Fig 5.
Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
V
CC
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
6. Functional description
Table 3.
Input
nA
L
X
H
[1]
Function table
[1]
Output
nB
X
L
H
nY
H
H
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
74HC_HCT00_Q100
All information provided in this document is subject to legal disclaimers.
1
1A
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 12 July 2012
3 of 15
NXP Semiconductors
74HC00-Q100; 74HCT00-Q100
Quad 2-input NAND gate
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
[1]
[1]
Min
0.5
-
-
-
-
50
65
[2]
Max
+7
20
20
25
50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO14 package: P
tot
derates linearly with 8 mW/K above 70
C.
For TSSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN14 packages: P
tot
derates linearly with 4.5 mW/K above 60
C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
74HC00-Q100
Min
2.0
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
74HCT00-Q100
Min
4.5
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
C
ns/V
ns/V
ns/V
Unit
74HC_HCT00_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 12 July 2012
4 of 15
NXP Semiconductors
74HC00-Q100; 74HCT00-Q100
Quad 2-input NAND gate
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74HC00-Q100
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
=
20 A;
V
CC
= 2.0 V
I
O
=
20 A;
V
CC
= 4.5 V
I
O
=
20 A;
V
CC
= 6.0 V
-
-
-
2.0
4.5
6.0
4.32
5.81
0
0
0
0.15
0.16
-
-
3.5
-
-
-
-
-
-
-
-
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
1
20
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1
40
-
V
V
V
V
V
V
V
V
V
V
A
A
pF
-
-
-
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
-
-
-
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
Conditions
Min
25
C
Typ
Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
I
O
=
4.0
mA; V
CC
= 4.5 V -
I
O
=
5.2
mA; V
CC
= 6.0 V -
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A;
V
CC
= 2.0 V
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 6.0 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
C
I
input leakage
current
supply current
input
capacitance
V
I
= V
CC
or GND;
V
CC
= 6.0 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
-
-
-
-
-
-
-
-
74HC_HCT00_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 12 July 2012
5 of 15
PCB设计
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