74HC05-Q100
Hex inverter with open-drain outputs
Rev. 1 — 9 July 2012
Product data sheet
1. General description
The 74HC05-Q100 is a high-speed Si-gate CMOS device that complies with JEDEC
standard no. 7A.
The 74HC05-Q100 contains six inverters. The outputs of the 74HC05-Q100 are
open-drain and can be connected to other open-drain outputs to implement active-LOW
wired-OR or active-HIGH wired-AND functions. The open-drain outputs require pull-up
resistors to perform correctly.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Wide operating voltage 2.0 V to 6.0 V
Input levels:
For 74HC05-Q100: CMOS level
Latch-up performance exceeds 100 mA per JESD 78 Class II level A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0
)
Multiple package options
NXP Semiconductors
74HC05-Q100
Hex inverter with open-drain outputs
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC05D-Q100
40 C
to +125
C
SO14
TSSOP14
DHVQFN14
Description
plastic small outline package; 14 leads; body width
3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
Type number
74HC05PW-Q100
40 C
to +125
C
74HC05BQ-Q100
40 C
to +125
C
plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
4. Functional diagram
1
1A
1Y 2
3
2A
2Y 4
5
3A
3Y 6
9
4A
4Y 8
V
CC
11
5A
5Y 10
Y
13
6A
6Y 12
A
GND
001aaj979
mna525
Fig 1.
Logic symbol
Fig 2.
Logic diagram (one gate)
74HC05_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 9 July 2012
2 of 15
NXP Semiconductors
74HC05-Q100
Hex inverter with open-drain outputs
5. Pinning information
5.1 Pinning
74HC05-Q100
1A
1Y
2A
2Y
3A
3Y
GND
1
2
3
4
5
6
7
aaa-003361
14 V
CC
13 6A
12 6Y
11 5A
10 5Y
9
8
4A
4Y
Fig 3.
Pin configuration SOT108-1 (SO14)
74HC05-Q100
terminal 1
index area
14 V
CC
13 6A
12 6Y
11 5A
GND
(1)
7
8
10 5Y
9
GND
4Y
4A
1A
2
3
4
5
6
1
1Y
14 V
CC
13 6A
12 6Y
11 5A
10 5Y
9
8
aaa-003362
74HC05-Q100
1A
1Y
2A
2Y
3A
3Y
GND
1
2
3
4
5
6
7
2A
2Y
3A
3Y
4A
4Y
aaa-003363
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 4.
Pin configuration SOT402-1 (TSSOP14)
Fig 5.
Pin configuration SOT762-1 (DHVQFN14)
5.2 Pin description
Table 2.
Symbol
1A to 6A
1Y to 6Y
GND
V
CC
Pin description
Pin
1, 3, 5, 9, 11, 13
2, 4, 6, 8, 10, 12
7
14
Description
data input
data output
ground (0 V)
supply voltage
74HC05_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 9 July 2012
3 of 15
NXP Semiconductors
74HC05-Q100
Hex inverter with open-drain outputs
6. Functional description
Table 3.
Input
nA
L
H
[1]
Function table
[1]
Output
nY
Z
L
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
< V
CC
+ 0.5 V
[1]
[1]
[1]
Min
0.5
-
-
0.5
-
-
50
65
[2]
Max
+7
±20
±20
25
50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
V
CC
+ 0.5 V V
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO14 package: P
tot
derates linearly with 8 mW/K above 70
C.
For TSSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN14 packages: P
tot
derates linearly with 4.5 mW/K above 60
C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol
V
CC
V
I
V
O
T
amb
t/V
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
Min
2.0
0
0
40
-
-
-
Typ
5.0
-
-
-
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
Unit
V
V
V
C
ns/V
ns/V
ns/V
74HC05_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 9 July 2012
4 of 15
NXP Semiconductors
74HC05-Q100
Hex inverter with open-drain outputs
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
Min
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A;
V
CC
= 2.0 V
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 6.0 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
OZ
input leakage
current
OFF-state
output current
V
I
= V
CC
or GND;
V
CC
= 6.0 V
per input pin; V
I
= V
IL
;
V
O
= V
CC
or GND;
other inputs at V
CC
or GND;
V
CC
= 6.0 V; I
O
= 0 A
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
-
-
-
-
-
-
-
-
-
0
0
0
0.15
0.16
-
-
0.1
0.1
0.1
0.26
0.26
±0.1
±0.5
-
-
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
±1
±5.0
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1
±10
V
V
V
V
V
A
A
1.5
3.15
4.2
-
-
-
25
C
Typ
1.2
2.4
3.2
0.8
2.1
2.8
Max
-
-
-
0.5
1.35
1.8
40 C
to +85
C 40 C
to +125
C
Unit
Min
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
Max
Min
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
Max
V
V
V
V
V
V
I
CC
C
I
supply current
input
capacitance
-
3.5
2.0
-
-
-
20
-
-
-
40
-
A
pF
74HC05_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 9 July 2012
5 of 15
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