74HC240-Q100; 74HCT240-Q100
Octal buffer/line driver; 3-state; inverting
Rev. 1 — 30 July 2012
Product data sheet
1. General description
The 74HC240-Q100; 74HCT240-Q100 is a high-speed Si-gate CMOS device and is pin
compatible with Low-Power Schottky TTL (LSTTL).
The 74HC240-Q100; 74HCT240-Q100 is a dual octal inverting buffer/line driver with
3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and
2OE. A HIGH on nOE causes the outputs to assume a high impedance OFF-state.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Inverting 3-state outputs
Multiple package options
Complies with JEDEC standard no. 7 A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC240D-Q100
74HCT240D-Q100
74HC240PW-Q100
74HCT240PW-Q100
74HC240BQ-Q100
74HCT240BQ-Q100
40 C
to +125
C
40 C
to +125
C
TSSOP20
40 C
to +125
C
Name
SO20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT360-1
Type number
DHVQFN20 plastic dual-in-line compatible thermal enhanced
SOT764-1
very thin quad flat package; no leads; 20 terminals;
body 2.5
4.5
0.85 mm
NXP Semiconductors
74HC240-Q100; 74HCT240-Q100
Octal buffer/line driver; 3-state; inverting
4. Functional diagram
2
1A0
1Y0
18
4
1A1
1Y1
16
6
1A2
1Y2
14
1
8
EN
18
16
14
12
15
17
1
1A3
1Y3
12
2
2
17
4
15
6
13
8
11
1
19
1A0
2A0
1A1
2A1
1A2
2A2
1A3
2A3
1OE
2OE
mgu779
1OE
1Y0 18
2Y0 3
1Y1 16
2Y1 5
4
6
8
2A0
2Y0
3
2A1
2Y1
5
19
1Y2 14
2Y2
7
11
1Y3 12
2Y3 9
13
15
17
EN
9
7
5
3
mgu778
13
2A2
2Y2
7
11
2A3
2Y3
9
19
2OE
mgu780
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Functional diagram
74HC_HCT240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 30 July 2012
2 of 16
NXP Semiconductors
74HC240-Q100; 74HCT240-Q100
Octal buffer/line driver; 3-state; inverting
5. Pinning information
5.1 Pinning
74HC240-Q100
74HCT240-Q100
1OE
2
3
4
5
6
7
8
9
GND 10
2A3 11
GND
(1)
1
terminal 1
index area
20 V
CC
19 2OE
18 1Y0
17 2A0
16 1Y1
15 2A1
14 1Y2
13 2A2
12 1Y3
74HC240-Q100
74HCT240-Q100
1OE
1A0
2Y0
1A1
2Y1
1A2
2Y2
1A3
2Y3
1
2
3
4
5
6
7
8
9
20 V
CC
19 2OE
18 1Y0
17 2A0
16 1Y1
15 2A1
14 1Y2
13 2A2
12 1Y3
11 2A3
aaa-003157
1A0
2Y0
1A1
2Y1
1A2
2Y2
1A3
2Y3
GND 10
aaa-003158
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration SO20, TSSOP20
Fig 5.
Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
1OE, 2OE
1A0, 1A1, 1A2, 1A3
2Y0, 2Y1, 2Y2, 2Y3
GND
2A0, 2A1, 2A2, 2A3
1Y0, 1Y1, 1Y2, 1Y3
V
CC
Pin description
Pin
1, 19
2, 4, 6, 8
3, 5, 7, 9
10
17, 15, 13, 11
18, 16, 14, 12
20
Description
output enable input (active LOW)
data input
bus output
ground (0 V)
data input
bus output
supply voltage
74HC_HCT240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 30 July 2012
3 of 16
NXP Semiconductors
74HC240-Q100; 74HCT240-Q100
Octal buffer/line driver; 3-state; inverting
6. Functional description
Table 3.
Input
nOE
L
L
H
[1]
Function table
[1]
Output
nAn
L
H
X
nYn
H
L
Z
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
Min
0.5
-
-
-
-
70
65
[1]
Max
+7
20
20
35
70
-
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
-
For SO20 packages: above 70
C,
P
tot
derates linearly with 8 mW/K.
For TSSOP20 package: above 60
C,
P
tot
derates linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60
C,
P
tot
derates linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
O
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
input transition rise and fall rate V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
T
amb
ambient temperature
Conditions
Min
2.0
0
0
-
-
-
40
Typ
5.0
-
-
-
1.67
-
-
Max
6.0
V
CC
V
CC
625
139
83
+125
Unit
V
V
V
ns/V
ns/V
ns/V
C
74HC240-Q100
74HC_HCT240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 30 July 2012
4 of 16
NXP Semiconductors
74HC240-Q100; 74HCT240-Q100
Octal buffer/line driver; 3-state; inverting
Table 5.
Symbol
V
CC
V
I
V
O
t/V
T
amb
Recommended operating conditions
…continued
Parameter
supply voltage
input voltage
output voltage
input transition rise and fall rate V
CC
= 4.5 V
ambient temperature
Conditions
Min
4.5
0
0
-
40
Typ
5.0
-
-
1.67
-
Max
5.5
V
CC
V
CC
139
+125
Unit
V
V
V
ns/V
C
74HCT240-Q100
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74HC240-Q100
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level
V
I
= V
IH
or V
IL
output voltage
I
O
=
20 A;
V
CC
= 2.0 V
I
O
=
20 A;
V
CC
= 4.5 V
I
O
=
20 A;
V
CC
= 6.0 V
I
O
=
6.0
mA; V
CC
= 4.5 V
I
O
=
7.8
mA; V
CC
= 6.0 V
V
OL
LOW-level
V
I
= V
IH
or V
IL
output voltage
I
O
= 20
A;
V
CC
= 2.0 V
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 6.0 V
I
O
= 6.0 mA; V
CC
= 4.5 V
I
O
= 7.8 mA; V
CC
= 6.0 V
I
I
I
OZ
input leakage
current
OFF-state
output current
V
I
= V
CC
or GND;
V
CC
= 6.0 V
per input pin; V
I
= V
IH
or V
IL
;
V
O
= V
CC
or GND;
other inputs at V
CC
or GND;
V
CC
= 6.0 V; I
O
= 0 A
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
1.2
2.4
3.2
0.8
2.1
2.8
2.0
4.5
6.0
-
-
-
0.5
1.35
1.8
-
-
-
-
-
0.1
0.1
0.1
0.26
0.26
0.1
0.5
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
1.0
5.0
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1.0
10
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A
A
Conditions
Min
25
C
Typ
Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
3.98 4.32
5.48 5.81
-
-
-
-
-
-
-
0
0
0
0.15
0.16
-
-
I
CC
C
I
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
input
capacitance
-
-
-
3.5
8.0
-
-
-
80
-
-
-
160
-
A
pF
74HC_HCT240_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 30 July 2012
5 of 16
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