74HC594-Q100; 74HCT594-Q100
8-bit shift register with output register
Rev. 1 — 2 August 2012
Product data sheet
1. General description
The 74HC594-Q100; 74HCT594-Q100 is a high-speed Si-gate CMOS device and is pin
compatible with Low-Power Schottky TTL (LSTTL).
The 74HC594-Q100; 74HCT594-Q100 is an 8-bit, non-inverting, serial-in, parallel-out shift
register that feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP)
and direct overriding clears (SHR and STR) are provided on both the shift and storage
registers. A serial output (Q7S) is provided for cascading purposes.
Both the shift and storage register clocks are positive-edge triggered. If both clocks are
connected together, the shift register is always one count pulse ahead of the storage
register.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Synchronous serial input and output
Complies with JEDEC standard No.7A
8-bit parallel output
Shift and storage registers have independent direct clear and clocks
Independent clocks for shift and storage registers
100 MHz (typical)
Multiple package options
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
3. Applications
Serial-to parallel data conversion
Remote control holding register
NXP Semiconductors
74HC594-Q100; 74HCT594-Q100
8-bit shift register with output register
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC594D-Q100
74HCT594D-Q100
40 C
to +125
C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
Version
SOT109-1
Type number
5. Functional diagram
DS
SHCP
SHR
14
11
10
9
12
13
8-BIT STORAGE REGISTER
Q7S
8-STAGE SHIFT REGISTER
STCP
STR
15 1
2
3
4
5
6
7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
mbc320
Fig 1.
Functional diagram
SHCP STCP
STR
11
12
9
15
1
2
DS
14
3
4
5
6
7
10
SHR
13
STR
mbc319
mbc322
13
12
10
11
14
R1 SRG8
C1/
1D
R2
C2
STCP
Q7S
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
DS
SHR
SHCP
2D
15
1
2
3
4
5
6
7
9
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q7S
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 August 2012
2 of 24
NXP Semiconductors
74HC594-Q100; 74HCT594-Q100
8-bit shift register with output register
STAGE 0
DS
D
Q
D
STAGES 1 TO 6
Q
STAGE 7
D
Q
Q7S
FFSH0
CP
R
SHCP
FFSH7
CP
R
SHR
D
Q
D
CP
Q
FFST0
CP
R
STCP
FFST7
R
STR
Q0
Q1 Q2 Q3 Q4 Q5 Q6
Q7
mbc321
Fig 4.
Logic diagram
SHCP
DS
STCP
SHR
STR
Q0
Q1
Q6
Q7
Q7S
mbc323
Fig 5.
Timing diagram
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 August 2012
3 of 24
NXP Semiconductors
74HC594-Q100; 74HCT594-Q100
8-bit shift register with output register
6. Pinning information
6.1 Pinning
74HC594-Q100
74HCT594-Q100
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
1
2
3
4
5
6
7
8
aaa-003475
16 V
CC
15 Q0
14 DS
13 STR
12 STCP
11 SHCP
10 SHR
9
Q7S
Fig 6.
Pin configuration SO16
6.2 Pin description
Table 2.
Symbol
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
GND
Q7S
SHR
SHCP
STCP
STR
DS
V
CC
Pin description
Pin
15, 1, 2, 3, 4, 5, 6, 7
8
9
10
11
12
13
14
16
Description
parallel data output
ground (0 V)
serial data output
shift register reset (active LOW)
shift register clock input
storage register clock input
storage register reset (active LOW)
serial data input
supply voltage
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 August 2012
4 of 24
NXP Semiconductors
74HC594-Q100; 74HCT594-Q100
8-bit shift register with output register
7. Functional description
Table 3.
Function
Clear shift register
Clear storage register
Load DS into shift register stage 0, advance previous stage data to the next stage
Transfer shift register data to storage register and outputs Qn
Shift register one count pulse ahead of storage register
[1]
Function table
[1]
Input
SHR
L
X
H
X
H
STR
X
L
X
H
H
SHCP STCP
X
X
X
X
X
X
DS
X
X
H or L
X
X
H = HIGH voltage level; L = LOW voltage level;
= LOW-to-HIGH transition; X = don’t care.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
Parameter
supply voltage
input clamping current
output clamping current
output current
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to V
CC
+ 0.5 V
Serial data output Q7S
Parallel data output
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[1]
[1]
Conditions
Min
0.5
-
-
-
-
-
-
-
-
65
[2]
Max
+7.0
20
20
25
35
50
70
50
70
+150
500
Unit
V
mA
mA
mA
mA
mA
mA
mA
mA
C
mW
supply current
ground current
storage temperature
total power dissipation
Serial data output Q7S
Parallel data output
Serial data output Q7S
Parallel data output
T
amb
=
40 C
to +125
C
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO16 packages: above 70
C
the value of P
tot
derates linearly with 8 mW/K.
74HC_HCT594_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 2 August 2012
5 of 24
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