WCMA2008U1B
WCMA2008U1B
256K x 8 Static RAM
Features
• High Speed
— 70ns availability
• Voltage range
— 2.7V–3.3V
• Ultra low active power
— Typical active current: 1 mA @ f = 1MHz
— Typical active current: 7 mA @ f = f
max
(70ns speed)
• Low standby power
• Easy memory expansion with CE
1
,CE
2
,and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
reduces power consumption by 80% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected (CE
1
HIGH or CE
2
LOW).
Writing to the device is accomplished by taking Chip Enable
(CE
1
) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE
2
) HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is
then written into the location specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip En-
able (CE
1
) and Output Enable (OE) LOW while forcing Write
Enable (WE) and Chip Enable 2 (CE
2
) HIGH. Under these
conditions, the contents of the memory location specified by
the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected ( E
1
C
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW and CE
2
HIGH and WE
LOW).
The WCMA2008U1B is available in a 36-ball FBGA package.
Functional Description
The WCMA2008U1B is a high-performance CMOS static
RAM organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is device is ideal for portable applications. The device
also has an automatic power-down feature that significantly
Logic Block Diagram
Data in Drivers
I/O
0
I/O
1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
A
19
0
A
11
ROW DECODER
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
128K x 8
ARRAY
CE
2
CE
1
WE
OE
COLUMN
DECODER
PO WER
DOWN
I/O
6
I/O
7
A
12
A
13
A
14
A
15
A
16
A
17
WCMA2008U1B
Pin Configurations
FBGA (Top View)
1
A
0
I/O
4
I/O
5
V
SS
V
CC
I/O
6
I/O
7
A
9
OE
A
10
NC
CE
1
A
11
A
17
A
16
A
12
A
15
A
13
2
A
1
A
2
3
CE
2
WE
DNU
4
A
3
A
4
A
5
5
A
6
A
7
6
A
8
I/O
0
I/O
1
V
CC
V
SS
I/O
2
I/O
3
A
14
A
B
C
D
E
F
G
H
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied...............................................55°C to +125°C
Supply Voltage to Ground Potential..... ..........–0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[1]
........................................0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
..................................–0.5V to V
CC
+ 0.5V
Output Current into Outputs (LOW)............................20 mA
Static Discharge Voltage ..........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ......................................................>200 mA
Operating Range
Product
WCMA2008U1B
Range
Industrial
Ambient Temperature
–40°C to +85°C
V
CC
2.7V to 3.3V
Product Portfolio
Power Dissipation (Industrial)
Product
Min.
WCMA2008U1B
2.7V
V
CC
Range
Typ.
[2]
Speed
Max.
3.3V
70 ns
Operating, I
CC
f = 1 MHz
Typ.
[2]
f = f
max
Typ.
[2]
Standby (I
SB2
)
Typ.
[2]
2
µA
Max.
10
µA
Max.
3 mA
Max.
15 mA
3.0V
1.5 mA
7 mA
Notes:
1. V
IL(min.)
= –2.0V for pulse durations less than 20 ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
, T
A
= 25°C.
2
WCMA2008U1B
Electrical Characteristics
Over the Operating Range
WCMA2008U1B-70
Param-
eter
V
OH
V
O L
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
V
CC
Operating Supply
Current
Automatic CE
Power-Down Current —
CMOS Inputs
Automatic CE
Power-Down Current—
CMOS Inputs
GND < V
I
< V
CC
f =f
MAX
= 1/t
RC
f = 1 MHz
V
CC
= 3.3V
I
OUT
= 0 mA
CMOS Levels
Output Leakage Current GND < V
O
< V
CC
, Output Disabled
Test Conditions
I
OH
= –1.0 mA
I
O L
= 2.1 mA
V
CC
= 2.7V
V
CC
= 2.7V
2.2
–0.3
–1
–1
7
1.5
2
Min.
2.4
0.4
V
CC
+ 0.3V
0.8
+1
+1
15
3
10
µA
Typ.
[2]
Max.
Unit
V
V
V
V
µA
µA
mA
I
SB1
CE
1
> V
CC
– 0.2V or CE
2
< 0.2V
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
f = f
max
(Address and Data Only),
f = 0 (OE,WE)
CE
1
> V
CC
– 0.2V or CE
2
< 0.2V
V
IN
> V
CC
−
0.2V or V
IN
< 0.2V,
f = 0, V
CC
=3.3V
I
SB2
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,V
CC
= Vcc
(typ)
Max.
6
8
Unit
pF
pF
Thermal Resistance
Description
Thermal Resistance
[3]
(Junction to Ambient)
Thermal Resistance
[3]
(Junction to Case)
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
Test Conditions
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer print-
ed circuit board
Symbol
Θ
JA
Θ
JC
BGA
55
16
Unit
°C/W
°C/W
3
WCMA2008U1B
AC Test Loads and Waveforms
R1
V
CC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
V
CC
Typ
10%
GND
Rise Time: 1 V/ns
Fall time: 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Equivalent to:
OUTPUT
THÉVENIN EQUIVALENT
R
TH
V
TH
Parameters
R1
R2
R
TH
V
TH
3.3V
1105
1550
645
1.75
Unit
Ohms
Ohms
Ohms
Volts
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
t
CDR[3]
t
R[4]
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery
Time
V
CC
= 1.5V
CE
1
> V
CC
– 0.2V or CE
2
< 0.2V
V
IN
> V
CC
−
0.2V or V
IN
< 0.2V
0
t
RC
Conditions
Min.
1.5
1
Typ.
[2]
Max.
V
ccmax
6
Unit
V
µA
ns
ns
Data Retention Waveform
DATA RETENTION MODE
V
CC
V
CC(min)
t
CDR
CE
1
V
DR
> 1.5 V
V
CC(min)
t
R
or
CE
2
Note:
4. Full Device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100
µs
or stable at V
CC(min.)
>
100
µs.
4
WCMA2008U1B
Switching Characteristics
Over the Operating Range
[5]
WCMA2008U1B-70
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
[8,]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE
1
LOW and CE
2
HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[6, 7]
WE HIGH to Low Z
[6]
10
70
60
60
0
0
50
30
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[6]
OE HIGH to High Z
[6, 7]
CE
1
LOW and CE
2
HIGH to Low Z
[6]
Description
Min.
70
Max.
Unit
ns
70
10
70
35
5
25
10
25
0
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE
1
HIGH or CE
2
LOW to High Z
[6, 7]
CE
1
LOW and CE
2
HIGH to Power-Up
CE
1
HIGH or CE
2
LOW to Power-Down
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
CC(typ.)
/2, input pulse levels of 0 to V
CC(typ.)
, and output loading
of the specified I
OL
/I
O H
and 30 pF load capacitance.
6. At any given temperature and voltage condition, t
H Z C E
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
8. The internal write time of the memory is defined by the overlap of WE, CE
1
= V
IL
, and CE
2
= V
IH
. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that
terminates the write.
5
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