74LVC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs;
positive-edge trigger; 3-state
Rev. 3 — 6 December 2012
Product data sheet
1. General description
The 74LVC374A is an octal D-type flip-flop featuring separate D-type inputs for each
flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an
outputs enable input (OE) are common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs that meet the set-up and
hold times requirements on the LOW-to-HIGH CP transition.
When pin OE is LOW, the contents of the eight flip-flops is available at the outputs. When
pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the flip-flops.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and 5 V applications.
The 74LVC374A is functionally identical to the 74LVC574A, but has a different pin
arrangement.
2. Features and benefits
5 V tolerant inputs/outputs; for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
High-impedance when V
CC
= 0 V
8-bit positive edge-triggered register
Independent register and 3-state buffer operation
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74LVC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC374AD
74LVC374ADB
40 C
to +125
C
40 C
to +125
C
Name
SO20
SSOP20
TSSOP20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT339-1
SOT360-1
SOT764-1
Type number
74LVC374APW
40 C
to +125
C
74LVC374ABQ
40 C
to +125
C
DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5
4.5
0.85 mm
4. Functional diagram
1
11
EN
C1
2
5
6
9
12
15
16
19
mna196
11
3
4
7
8
13
14
17
18
CP
D0
D1
D2
D3
D4
D5
D6
D7
OE
1
mna891
3
1D
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
4
7
8
13
14
17
18
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVC374A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 6 December 2012
2 of 19
NXP Semiconductors
74LVC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
3
4
7
8
13
14
17
18
D0
D1
D2
D3
D4
D5
D6
D7
FF1
to
FF8
3-STATE
OUTPUTS
Q0
Q1
Q2
Q3
2
5
6
9
Q4 12
Q5 15
Q6 16
Q7 19
11 CP
1 OE
mna892
Fig 3.
Functional diagram
D0
D1
D2
D3
D4
D5
D6
D7
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
FF1
FF2
FF3
FF4
FF5
FF6
FF7
FF8
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna893
Fig 4.
Logic diagram
74LVC374A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 6 December 2012
3 of 19
NXP Semiconductors
74LVC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
5. Pinning information
5.1 Pinning
terminal 1
index area
Q0
D0
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
001aad040
2
3
4
5
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
CP 11
D1
Q1
Q2
D2
D3
Q3
6
7
8
9
GND 10
GND
(1)
374
1
OE
374
GND 10
001aad088
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration for SO20 and (T)SSOP20
Fig 6.
Pin configuration for DHVQFN20
5.2 Pin description
Table 2.
Symbol
1
Q[0:7]
D[0:7]
10
11
20
Pin description
Pin
OE
2, 5, 6, 9, 12, 15, 16, 19
3, 4, 7, 8, 13, 14, 17, 18
GND
CP
V
CC
Description
output enable input (active LOW)
3-state flip-flop output
data input
ground (0 V)
clock input (LOW-to-HIGH, edge-triggered)
supply voltage
74LVC374A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 6 December 2012
4 of 19
NXP Semiconductors
74LVC374A
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
6. Functional description
Table 3.
Function table
[1]
Input
OE
Load and read register
Load register and disable
outputs
[1]
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
Z = high-impedance OFF-state
= LOW-to-HIGH clock transition
Operating mode
Internal flip-flop Output
CP
Dn
l
h
l
h
L
H
L
H
Qn
L
H
Z
Z
L
L
H
H
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[2]
[2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
+6.5
50
100
-
+150
500
Unit
V
mA
V
mA
V
V
mA
mA
mA
C
mW
V
O
> V
CC
or V
O
< 0 V
output HIGH or LOW state
output 3-state
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
65
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO20 packages: above 70
C
the value of P
tot
derates linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60
C
the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60
C
the value of P
tot
derates linearly with 4.5 mW/K.
74LVC374A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 6 December 2012
5 of 19
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