Si550
R
EVISION
D
V
O L TA G E
- C
O N T R O L L E D
C
R Y S TA L
O
S C I L L A T O R
(VCXO)
10 MH
Z T O
1.4 G H
Z
Features
Available with any-rate output
frequencies from 10 to 945 MHz
and selected frequencies to
1.4 GHz
3rd generation DSPLL
®
with
superior jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Lead-free/RoHS-compliant
Si5602
Ordering Information:
See page 8.
Applications
SONET/SDH
xDSL
10 GbE LAN/WAN
Low-jitter clock generation
Optical modules
Clock and data recovery
Pin Assignments:
See page 7.
(Top View)
V
C
1
2
3
6
5
4
V
DD
Description
The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry to
provide a low-jitter clock at high frequencies. The Si550 is available with
any-rate output frequency from 10 to 945 MHz and selected frequencies to
1400 MHz. Unlike traditional VCXOs, where a different crystal is required for
each output frequency, the Si550 uses one fixed crystal to provide a wide
range of output frequencies. This IC-based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In
addition, DSPLL clock synthesis provides superior supply noise rejection,
simplifying the task of generating low-jitter clocks in noisy environments
typically found in communication systems. The Si550 IC-based VCXO is
factory-configurable for a wide variety of user specifications, including
frequency, supply voltage, output format, tuning slope, and temperature
stability. Specific configurations are factory programmed at time of shipment,
thereby eliminating the long lead times associated with custom oscillators.
OE
GND
CLK–
CLK+
Functional Block Diagram
V
DD
CLK–
CLK+
Fixed
Frequency
XO
Any-rate
10-1400 MHz
DSPLL
®
Clock Synthesis
ADC
Vc
OE
GND
Rev. 0.6 6/07
Copyright © 2007 by Silicon Laboratories
Si550
Si550
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage
1
Symbol
V
DD
Test Condition
3.3 V option
2.5 V option
1.8 V option
Supply Current
I
DD
Output enabled
LVPECL
CML
LVDS
CMOS
tristate mode
Output Enable (OE)
2
Operating Temperature Range
T
A
V
IH
V
IL
Min
2.97
2.25
1.71
—
—
—
—
—
0.75 x V
DD
—
–40
Typ
3.3
2.5
1.8
120
108
99
90
60
—
—
—
Max
3.63
2.75
1.89
130
117
108
98
75
—
0.5
85
V
°C
V
Units
mA
Notes:
1.
Selectable parameter specified by part number. See 3. "Ordering Information" on page 8 for further details.
2.
OE pin includes a 17 kΩ resistor to V
DD
.
Table 2. V
C
Control Voltage Input
Parameter
Control Voltage Tuning Slope
1,2,3
Symbol
K
V
Test Condition
10 to 90% of V
DD
Min
—
Typ
33
45
90
135
180
356
±1
±5
10.0
—
V
DD
/2
Max
—
Units
ppm/V
Control Voltage Linearity
4
Modulation Bandwidth
V
C
Input Impedance
Nominal Control Voltage
Control Voltage Tuning Range
L
VC
BW
Z
VC
V
CNOM
V
C
BSL
Incremental
–5
–10
9.3
500
+5
+10
10.7
—
—
V
DD
%
kHz
kΩ
V
V
@ f
O
—
0
Notes:
1.
Positive slope; selectable option by part number. See 3. "Ordering Information" on page 8.
2.
For best jitter and phase noise performance, always choose the smallest K
V
that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K
V
), Stability, and Absolute Pull Range (APR)” for more information.
3.
K
V
variation is ±10% of typical values.
4.
BSL determined from deviation from best straight line fit with V
C
ranging from 10 to 90% of V
DD
. Incremental slope
determined with V
C
ranging from 10 to 90% of V
DD
.
2
Rev. 0.6
Si550
Table 3. CLK± Output Frequency Characteristics
Parameter
Nominal Frequency
1,2,3
Temperature Stability
1,4
Symbol
f
O
Test Condition
LVDS/CML/LVPECL
CMOS
T
A
= –40 to +85 ºC
Min
10
10
–20
–50
–100
±25
Frequency drift over first year.
Frequency drift over 15 year life.
Power up Time
5
t
OSC
Typ
—
—
—
—
—
—
—
—
—
Max
945
160
+20
+50
+100
±375
±3
±10
10
Units
MHz
ppm
ppm
ppm
ms
Absolute Pull Range
1,4
Aging
APR
—
—
—
Notes:
1.
See Section 3. "Ordering Information" on page 8 for further details.
2.
Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3.
Nominal output frequency set by V
CNOM
= V
DD
/2.
4.
Selectable parameter specified by part number.
5.
Time from power up or tristate mode to f
O
.
Table 4. CLK± Output Levels and Symmetry
Parameter
LVPECL Output Option
1
Symbol
V
O
V
OD
V
SE
Test Condition
mid-level
swing (diff)
swing (single-ended)
mid-level
swing (diff)
Min
V
DD
– 1.42
1.1
0.55
1.125
0.5
Typ
—
Max
V
DD
– 1.25
1.9
0.95
1.275
0.9
Units
V
V
PP
V
PP
V
V
PP
—
—
1.20
0.7
LVDS Output Option
2
V
O
V
OD
CML Output Option
2
CMOS Output Option
3
Rise/Fall time (20/80%)
Symmetry (duty cycle)
V
O
V
OD
V
OH
V
OL
t
R,
t
F
mid-level
swing
(diff)
I
OH
= 32 mA
I
OL
= 32 mA
—
0.70
0.8 x V
DD
V
DD
– 0.75
0.95
—
—
—
1
—
—
1.20
V
DD
V
V
PP
V
—
—
—
45
0.4
350
—
55
LVPECL/LVDS/CML
CMOS with C
L
= 15 pF
LVPECL:
LVDS:
CMOS:
V
DD
– 1.3 V (diff)
1.25 V (diff)
V
DD
/2
ps
ns
%
SYM
Notes:
1.
50
Ω
to V
DD
– 2.0 V.
2.
R
term
= 100
Ω
(differential).
3.
C
L
= 15 pF
Rev. 0.6
3
Si550
Table 5. CLK± Output Phase Jitter
Parameter
Phase Jitter (RMS)
1,2,3
for F
OUT
> 500 MHz
Symbol
Test Condition
Kv = 33 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Min
—
—
—
—
—
—
—
—
—
—
—
—
Typ
0.26
0.26
0.27
0.26
0.32
0.26
0.40
0.27
0.49
0.28
0.87
0.33
Max
—
—
—
—
—
—
—
—
—
—
—
—
Units
ps
φ
J
Notes:
1.
Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
2.
For best jitter and phase noise performance, always choose the smallest K
V
that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K
V
), Stability, and Absolute Pull Range (APR)” for more information.
3.
See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
4
Rev. 0.6
Si550
Table 5. CLK± Output Phase Jitter (Continued)
Parameter
Phase Jitter (RMS)
1,2,3
for F
OUT
of 125 to 500 MHz
Symbol
Test Condition
Kv = 33 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
Min
—
—
—
—
—
—
—
—
—
—
—
—
Typ
0.37
0.33
0.37
0.33
0.43
0.34
0.50
0.34
0.59
0.35
1.00
0.39
Max
—
—
—
—
—
—
—
—
—
—
—
—
Units
ps
φ
J
Notes:
1.
Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
2.
For best jitter and phase noise performance, always choose the smallest K
V
that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K
V
), Stability, and Absolute Pull Range (APR)” for more information.
3.
See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
Table 6. CLK± Output Period Jitter
Parameter
Period Jitter*
Symbol
J
PER
Test Condition
RMS
Peak-to-Peak
Min
—
—
Typ
2
14
Max
—
—
Units
ps
*Note:
Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Rev. 0.6
5
FPGA/CPLD
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