OL2311
Highly integrated single-chip sub 1 GHz RF receiver
Rev. 1 — 8 December 2011
Product data sheet
1. General description
A highly integrated single-chip receiver solution, the OL2311 is ideally suited to telemetry
applications operating in the ISM/SRD bands. The small form factor, low power
consumption and wide supply voltage range make this device suitable for use in battery
powered, handheld devices and their counter parts.
The device utilizes a fully integrated, programmable fractional-N PLL (including loop filter)
to control the Local Oscillator (LO), thus supporting multi-channel operation and
frequency hopping schemes. This feature also allows programmable frequency steps for
crystal (XTAL) drift compensation.
The device is based on a low IF direct conversion receiver architecture, with on-chip IF
filtering and programmable channel bandwidth. After filtering and amplification the
quadrature signals are digitized, demodulated and processed in the digital domain.
Baseband processing of the received signal comprises a demodulator, a data-slicer and
clock recovery followed by a Manchester decoder. Automated signal signature recognition
units are available to allow simple, fast and reliable data reception.
The device is controlled via a three-wire serial interface (SPI) with data input and output,
data clock and interface enable. The interface can be configured to a full SPI interface
with separate data and clock pins. Additional pins are available to access internal signals
in real-time.
2. Features and benefits
Highly integrated solution for the 315/434/868/915 MHz band
Very few external components required
Complies with ETSI EN300-220/FCC part 15 standards
Near zero-IF RX architecture
On-chip channel filtering with automatic calibration supported to provide stable cut-off
frequencies and filter roll-off
Multi-channel operation by fully integrated fractional-N PLL with on-chip loop filter
Automatic VCO sub-band selection and calibration to reduce PLL loop bandwidth
variation
Digital RSSI with a configurable threshold
Onboard Signal Signature Recognition Unit with Preamble Pattern Recognition
Configurable polling timer with 2% absolute accuracy
Level Sensitive Data slicer with self-adjusting threshold
Low power Consumption (RX 16mA), with ultra Low 0.5µA standby current and
configurable polling timer
NXP Semiconductors
OL2311
Highly integrated single-chip sub 1 GHz RF receiver
Single Lithium cell operation (2.1V). Operation up to 3.6V fully supported
32-Pin HVQFN32 Pb-free package
3. Applications
Smart metering (wireless M-bus)
Home and building security and automation (KNX-RF)
Remote control devices
After-market Remote Keyless Entry (RKE)
Wireless medical applications
Wireless sensor network
4. Ordering information
Table 1.
Ordering information
Package
Name
OL2311AHN
HVQFN32
Description
plastic thermal enhanced very thin quad flat package; no leads; 32
terminals; body 5
5
0.85 mm
Version
SOT617-3
Type number
OL2311
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 8 December 2011
2 of 133
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Product data sheet
Rev. 1 — 8 December 2011
3 of 133
OL2311
5. Block diagram
NXP Semiconductors
SIGNAL SIGNATURE RECOGNITION UNIT
BAUD-RATE
GENERATOR
POLLING
TIMER
P11/INT
RSSI LEVEL
CLASSIFICATION
MODULATION
AMPLITUDE
CLASSIFICATION
TIMING
CLASSIFICATION
PREAMBLE
DETECTION
UNIT
P14/IND
TEN
CHANNEL FILTER
AUTO CALIBRATION
RECEIVE
STATE MACINE
limiter
LNA
CHANNEL
FILTER
limiter
RF_IN
50 kHz to
300 kHz
RSSI
FM
DEMOD
FSK
DATA
FILTER
LEVEL
SLICER
EDGE
SLICER
CLOCK
RECOVERY
MANCHESTER
DECODER
P12/CLOCK
P13/SDO
ASK
RSSI
All information provided in this document is subject to legal disclaimers.
P10/DATA
BASEBAND PROCESSING
SEN
SDIO
CONTROL LOGIC, GAIN
SPI
SCLK
PTDIS
RESET
GENERATOR
REG
DIG
REG
PLL
optionally
to P12
buffer
VCO
AUTO
CALIBRATION
NUM/FRACTIONAL-N PLL
PFD
VREG_DIG
(digital supply)
VREG_PLL
(PLL supply)
VREG_VCO
(VCO supply)
Highly integrated single-chip sub 1 GHz RF receiver
MAIN DIVIDER
loop filter
REG
VCO
90 °
0°
÷2
OR
÷4
VCO
CHARGE
PUMP
XTAL
OSCILLATOR
XTAL1
GND_LNA
GND_REG_PLL
GND_DIG
GND_PLL
GND_REG_VCO
VCC_RF
GND_XO
VCC_IF
GND_RING
GND_VCO
VCC_DIG
VCC_XO
VCC_REG
GND_RF
GND_IF
exposed
die pad
XTAL2
TEST3
TEST2
TEST1
© NXP B.V. 2011. All rights reserved.
OL2311
001aan713
(1) All internal domain grounds including external GND pins 1, 8, 9, 16 and 32 are connected to the exposed die pad.
Fig 1.
Block diagram
NXP Semiconductors
OL2311
Highly integrated single-chip sub 1 GHz RF receiver
6. Pinning information
6.1 Pinning
30 VREG_PLL
31 VCC_REG
26 VCC_XO
27 RSTDIS
29 TEST3
terminal 1
index area
GND
VREG_VCO
VCC_IF
TEST1
TEST2
VCC_RF
RF_IN
GND
1
2
3
4
5
6
7
8
25 XTAL1
24 XTAL2
23 P13/SDO
22 P12/CLOCK
21 P11/INT
20 P10/DATA
19 SCLK
18 SDIO
17 SEN
GND 16
001aan712
32 GND
OL2311
n.c. 10
n.c. 11
n.c. 12
VREG_DIG 13
28 TEN
VCC_DIG 14
Transparent top view
Fig 2.
Pin configuration
6.2 Pin description
Table 2.
Symbol
GND
VREG_VCO
VCC_IF
TEST1
TEST2
VCC_RF
RF_IN
GND
GND
n.c.
n.c.
n.c.
VREG_DIG
VCC_DIG
P14/PIND
GND
OL2311
Pin description
Pin Type
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
-
A
A
A
A
A
A
-
-
A
A
A
A
A
DO
-
Reset
state
-
Z
A
Z
Z
A
A
-
-
Z
Z
A
A
A
Z
-
Description
ground; use exposed heatsink as ground reference
VCO regulator output voltage to decoupling capacitor
IF section power supply
RX test I output
RX test Q output
LNA power supply
RX RF signal input
ground; use exposed heatsink as ground reference
ground; use exposed heatsink as ground reference
not connected
not connected
not connected
digital regulator output voltage to decoupling capacitor
digital module supply voltage
digital output port with increased drive capability for PIN
diode control
ground; use exposed heatsink as ground reference
© NXP B.V. 2011. All rights reserved.
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 1 — 8 December 2011
P14/PIND 15
GND
9
4 of 133
NXP Semiconductors
OL2311
Highly integrated single-chip sub 1 GHz RF receiver
Pin description
…continued
Pin Type
17
18
19
20
21
DI
DIO
DIO
DIeO
DO
Reset
state
DI
DI
DI
Z
POR,
interrupt
output
1 MHz
reference
clock
Z
A
A
A
DI
DI
Z
Z
A
-
GND
Description
serial interface enable
serial interface input/output
serial interface clock
digital output port, RX data output, data output of debug
interface
digital output port, interrupt output, several status
indicators, reference clock output, frame indicator of
debug interface
digital output port, RX data clock, clock of debug interface
Table 2.
Symbol
SEN
SDIO
SCLK
P10/DATA
P11/INT
P12/CLOCK
22
DO
P13/SDO
XTAL2
XTAL1
VCC_XO
RSTDIS
TEN
TEST3
VREG_PLL
VCC_REG
GND
exposed die
pad
[1]
A = analog.
23
24
25
26
27
28
29
30
31
32
-
DO
A
A
A
DI
DI
A
A
A
-
A
digital output port, status indicators, serial interface data
output
crystal reference clock frequency input
crystal connection
crystal oscillator supply voltage
reset disable signal
test enable input
PLL test output
PLL regulator output voltage to decoupling capacitor
PLL, VCO regulators power supply
ground; use exposed heatsink as ground reference
ground connection
DI = digital input.
DO = digital output with enable signal.
DIO = digital input without enable signal and output with enable signal.
DIeO = digital input and output both with enable signal.
7. Functional description
7.1 General architecture description
The OL2311 receiver is designed for use in both complex base-stations, when paired with
powerful microcontrollers, and low component-count remote units with low pin-count
microcontrollers. The IC features unique configuration possibilities via external pin-level
configuration or SFR bit manipulation. Several automatic sequences are implemented to
ease device operation, all of which can be manually influenced or overridden by
control-bits.
OL2311
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 8 December 2011
5 of 133
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