74LVC1G123
Single retriggerable monostable multivibrator; Schmitt trigger
inputs
Rev. 2 — 1 August 2012
Product data sheet
1. General description
The 74LVC1G123 is a single retriggerable monostable multivibrator with Schmitt trigger
inputs. Output pulse width is controlled by three methods:
1. The basic pulse is programmed by selection of an external resistor (R
EXT
) and
capacitor (C
EXT
).
2. Once triggered, the basic output pulse width may be extended by retriggering the
gated active LOW-going edge input (A) or the active HIGH-going edge input (B). By
repeating this process, the output pulse period (Q = HIGH) can be made as long as
desired. Alternatively an output delay can be terminated at any time by a LOW-going
edge on input CLR, which also inhibits the triggering.
3. An internal connection from CLR to the input gates makes it possible to trigger the
circuit by a HIGH-going signal at input CLR.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment. Schmitt trigger inputs,
makes the circuit highly tolerant to slower input rise and fall times.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
DC triggered from active HIGH or active LOW inputs
Retriggerable for very long pulses up to 100 % duty factor
Direct reset terminates output pulse
Schmitt trigger on all inputs
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
Power-on-reset on outputs
Latch-up performance exceeds 100 mA
Direct interface with TTL levels
NXP Semiconductors
74LVC1G123
Single retriggerable monostable multivibrator; Schmitt trigger inputs
Inputs accept voltages up to 5.5 V
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVC1G123DP
74LVC1G123DC
74LVC1G123GT
74LVC1G123GF
74LVC1G123GD
74LVC1G123GM
74LVC1G123GN
74LVC1G123GS
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Description
Version
SOT505-2
SOT765-1
SOT833-1
SOT1089
TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
VSSOP8 plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
XSON8
XSON8
plastic extremely thin small outline package;
no leads; 8 terminals; body 1
1.95
0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35
1
0.5 mm
Type number
XSON8U plastic extremely thin small outline package; no
SOT996-2
leads; 8 terminals; UTLP based; body 3
2
0.5 mm
XQFN8
XSON8
XSON8
plastic extremely thin quad flat package; no leads;
8 terminals; body 1.6
1.6
0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.2
1.0
0.35 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35
1.0
0.35 mm
SOT902-2
SOT1116
SOT1203
4. Marking
Table 2.
Marking codes
Marking code
[1]
Y3
Y3
Y3
Y3
Y3
Y3
Y3
Y3
Type number
74LVC1G123DP
74LVC1G123DC
74LVC1G123GT
74LVC1G123GF
74LVC1G123GD
74LVC1G123GM
74LVC1G123GN
74LVC1G123GS
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
74LVC1G123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 1 August 2012
2 of 32
NXP Semiconductors
74LVC1G123
Single retriggerable monostable multivibrator; Schmitt trigger inputs
5. Functional diagram
CEXT
6
REXT/CEXT
1
A
Q
2
B
Q
7
5
3
CLR
R
aaa-001871
Fig 1.
Logic symbol
V
CC
REXT/CEXT
CEXT
CLR
R
CL
V
CC
V
CC
R
R
CL
Q
CL
A
CL
CL
B
R
aaa-001872
Fig 2.
Logic diagram
74LVC1G123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 1 August 2012
3 of 32
NXP Semiconductors
74LVC1G123
Single retriggerable monostable multivibrator; Schmitt trigger inputs
6. Pinning information
6.1 Pinning
74LVC1G123
A
1
8
V
CC
74LVC1G123
A
B
CLR
GND
1
2
3
4
aaa-001873
B
2
7
REXT/CEXT
8
7
6
5
V
CC
REXT/CEXT
CEXT
Q
CLR
3
6
CEXT
GND
4
5
Q
aaa-001874
Transparent top view
Fig 3.
Pin configuration SOT505-2 and SOT765-1
Fig 4.
Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
74LVC1G123
terminal 1
index area
V
CC
1
8
74LVC1G123
A
B
CLR
GND
1
2
3
4
8
7
6
5
V
CC
REXT/CEXT
7
A
CEXT
REXT/CEXT
CEXT
Q
Q
2
6
B
3
4
5
CLR
GND
aaa-001876
aaa-001875
Transparent top view
Transparent top view
Fig 5.
Pin configuration SOT996-2
Fig 6.
Pin configuration SOT902-1
74LVC1G123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 1 August 2012
4 of 32
NXP Semiconductors
74LVC1G123
Single retriggerable monostable multivibrator; Schmitt trigger inputs
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT902-2
SOT996-2, SOT1116 and SOT1203
A
B
CLR
GND
Q
CEXT
V
CC
1
2
3
4
5
6
8
7
6
5
4
3
2
1
8
negative-edge triggered input
positive-edge triggered input
direct reset LOW and positive-edge triggered
input
ground (0 V)
active HIGH output
external capacitor connection
external resistor and capacitor connection
supply voltage
Description
REXT/CEXT 7
7. Functional description
Table 4.
Input
CLR
L
X
X
H
H
[1]
Function table
[1]
Output
A
X
H
X
L
L
B
X
X
L
H
H
Q
L
L
[2]
L
[2]
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= LOW-to-HIGH transition;
= HIGH-to-LOW transition;
= one HIGH level output pulse;
= one LOW level output pulse.
[2]
If the monostable was triggered before this condition was established, the pulse continues as programmed.
74LVC1G123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 1 August 2012
5 of 32
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