TO
-92
MAC97A8; MAC97A6
Logic level triac
Rev. 2 — 14 September 2011
Product data sheet
1. Product profile
1.1 General description
Logic level sensitive gate triac intended to be interfaced directly to microcontrollers, logic
integrated circuits and other low power gate trigger circuits.
Product availability:
MAC97A8 in SOT54 (TO-92)
MAC97A6 in SOT54 (TO-92).
1.2 Features and benefits
Blocking voltage to 600 V (MAC97A8)
Sensitive gate in all four quadrants
RMS on-state current to 0.6 A
Low cost package.
1.3 Applications
General purpose bidirectional switching
Phase control applications
Solid state relays.
1.4 Quick reference data
Table 1.
V
DRM
Quick reference data
Conditions
T
j
= 25 to 125
C
T
j
= 25 to 125
C
full sine wave; T
lead
50
C;
Figure 5
Typ
Max
600
400
0.6
8.0
Unit
V
V
A
A
repetitive peak off-state voltage
MAC97A8
MAC97A6
I
T(RMS)
I
TSM
on-state current (RMS value)
non-repetitive peak on-state current
Symbol Parameter
NXP Semiconductors
MAC97A8; MAC97A6
Logic level triac
2. Pinning information
Table 2.
Pin
1
2
3
Pinning - SOT54 (TO-92), simplified outline and symbol
Description
main terminal 2
gate
main terminal 1
1
2
3
1
Simplified outline
Symbol
2
msb033
3
mbl305
SOT54 (TO-92)
3. Ordering information
Table 3.
Ordering information
Package
Name
MAC97A8
MAC97A6
TO-92
TO-92
Description
Plastic single-ended leaded (through hole) package; 3 leads
Plastic single-ended leaded (through hole) package; 3 leads
Version
SOT54
SOT54
Type number
MAC97A8_A6
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 14 September 2011
2 of 13
NXP Semiconductors
MAC97A8; MAC97A6
Logic level triac
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DRM
repetitive peak off-state voltage
MAC97A8
MAC97A6
I
T(RMS)
I
TSM
on-state current (RMS value)
non-repetitive peak on-state current
T
j
= 25 to 125
C
T
j
= 25 to 125
C
full sine wave; T
lead
50
C;
Figure 5
full sine wave; T
j
= 25
C
prior to surge
t = 20 ms
t = 16.7 ms
I
2
t
dI
T
/dt
I
2
t for fusing
repetitive rate of rise of on-state
current after triggering
t
½
10 ms
I
TM
= 1.0 A; I
G
= 0.2 A; dI
G
/dt = 0.2 A/s
T2+ G+
T2+ G
T2 G
T2 G+
I
GM
V
GM
P
GM
P
G(AV)
T
stg
T
j
gate current (peak value)
gate voltage (peak value)
gate power (peak value)
average gate power
storage temperature
operating junction temperature
t = 2
s
max
t = 2
s
max
t = 2
s
max
T
case
= 80
C;
t = 2
s
max
40
40
50
50
50
10
1
5
5
0.1
+150
+125
A/s
A/s
A/s
A/s
V
W
W
C
C
8.0
8.8
0.32
A
A
A
2
s
600
400
0.6
V
V
A
Conditions
Min
Max
Unit
MAC97A8_A6
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 14 September 2011
3 of 13
NXP Semiconductors
MAC97A8; MAC97A6
Logic level triac
5. Thermal characteristics
Table 5.
Symbol
R
th(j-lead)
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from junction to lead
thermal resistance from junction to ambient
Conditions
full cycle
half cycle
mounted on a printed circuit board;
lead length = 4 mm;
Figure 1
Value
60
80
150
Unit
K/W
K/W
K/W
5.1 Transient thermal impedance
10
3
Z
th(j-a)
(K/W)
10
2
003aaa029
10
P
t
p
t
1
10
-5
10
-4
10
-3
10
-2
10
-1
1
t
p
(s)
10
Fig 1.
Transient thermal impedance from junction to ambient as a function of pulse duration.
MAC97A8_A6
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 14 September 2011
4 of 13
NXP Semiconductors
MAC97A8; MAC97A6
Logic level triac
6. Characteristics
Table 6.
Characteristics
T
j
= 25
C unless otherwise specified
Symbol
I
GT
Parameter
gate trigger current
Conditions
V
D
= 12 V; I
T
= 0.1 A;
Figure 8
T2+ G+
T2+ G
T2 G
T2 G+
I
L
latching current
V
D
= 12 V; I
GT
= 0.1 A;
Figure 9
T2+ G+
T2+ G
T2 G
T2 G+
I
H
V
T
V
GT
I
D
dV
D
/dt
holding current
on-state voltage
gate trigger voltage
off-state leakage current
critical rate of rise of
off-state voltage
V
D
= 12 V; I
GT
= 0.1 A;
Figure 10
I
T
= 0.85 A;
Figure 11
V
D
= 12 V; I
T
= 0.1 A;
Figure 7
V
D
= V
DRM
; I
T
= 0.1 A; T
j
= 110
C
V
D
= V
DRM (max)
; T
j
= 110
C
V
D
= 67% of V
DM(max)
;
T
case
= 110
C;
exponential
waveform; gate open circuit;
Figure 12
V
D
= rated V
DRM
; T
case
= 50
C;
I
TM
= 0.84 A;
commutating dI/dt = 0.3 A/ms
I
TM
= 1.0 A; V
D
= V
DRM(max)
;
I
G
= 25 mA; dI
G
/dt = 5 A/s
Dynamic characteristics
30
45
V/s
0.1
1
5
1
2
1
1.4
0.9
0.7
3
10
10
10
10
10
1.9
2
100
mA
mA
mA
mA
mA
V
V
V
A
1
2
2
4
5
5
5
7
mA
mA
mA
mA
Min
Typ
Max
Unit
Static characteristics
dV
com
/dt
critical rate of rise of
commutation voltage
gate controlled turn-on
time
5
V/s
t
gt
2
s
MAC97A8_A6
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 14 September 2011
5 of 13
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