SN54AC74, SN74AC74
DUAL POSITIVE EDGE TRIGGERED D TYPE FLIP FLOPS
WITH CLEAR AND PRESET
SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003
D
2-V to 6-V V
CC
Operation
D
Inputs Accept Voltages to 6 V
D
Max t
pd
of 10 ns at 5 V
description/ordering information
The ’AC74 devices are dual positive-edge-
triggered D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) input
sets or resets the outputs, regardless of the levels
of the other inputs. When PRE and CLR are
inactive (high), data at the data (D) input meeting
the setup-time requirements is transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold-time interval, data
at D can be changed without affecting the levels
at the outputs.
SN54AC74 . . . J OR W PACKAGE
SN74AC74 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
SN54AC74 . . . FK PACKAGE
(TOP VIEW)
1CLK
NC
1PRE
NC
1Q
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
1D
1CLR
NC
VCC
2CLR
2D
NC
2CLK
NC
2PRE
NC − No internal connection
ORDERABLE
PART NUMBER
SN74AC74N
SN74AC74D
SN74AC74DR
SN74AC74NSR
SN74AC74DBR
SN74AC74PW
SN74AC74PWR
SNJ54AC74J
SNJ54AC74W
SNJ54AC74FK
AC74
SNJ54AC74J
SNJ54AC74W
SNJ54AC74FK
AC74
AC74
AC74
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
ORDERING INFORMATION
TA
PDIP − N
SOIC − D
−40°C to 85 C
−40 C 85°C
SOP − NS
SSOP − DB
TSSOP − PW
CDIP − J
−55°C to 125 C
−55 C 125°C
CFP − W
LCCC − FK
PACKAGE†
Tube
Tube
Tape and reel
Tape and reel
Tape and reel
Tube
Tape and reel
Tube
Tube
Tube
TOP-SIDE
MARKING
SN74AC74N
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1Q
GND
NC
2Q
2Q
1
SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003
SN54AC74, SN74AC74
DUAL POSITIVE EDGE TRIGGERED D TYPE FLIP FLOPS
WITH CLEAR AND PRESET
FUNCTION TABLE
INPUTS
PRE
L
H
L
H
H
H
CLR
H
L
L
H
H
H
CLK
X
X
X
↑
↑
L
D
X
X
X
H
L
X
OUTPUTS
Q
H
L
H†
H
L
Q0
Q
L
H
H†
L
H
Q0
† This configuration is unstable; that is, it does not
persist when either PRE or CLR returns to its
inactive (high) level.
logic diagram, each flip-flop (positive logic)
PRE
CLK
C
C
TG
C
C
C
D
TG
TG
TG
C
Q
C
Q
C
CLR
C
C
2
POST OFFICE BOX 655303
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DALLAS, TEXAS 75265
SN54AC74, SN74AC74
DUAL POSITIVE EDGE TRIGGERED D TYPE FLIP FLOPS
WITH CLEAR AND PRESET
SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Output voltage range, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±200
mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54AC74
MIN
VCC
VIH
Supply voltage
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 3 V
VIL
VI
VO
IOH
Low-level input voltage
Input voltage
Output voltage
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 3 V
IOL
∆t/∆v
Low-level output current
Input transition rise or fall rate
VCC = 4.5 V
VCC = 5.5 V
VCC = 4.5 V
VCC = 5.5 V
0
0
2
2.1
3.15
3.85
0.9
1.35
1.65
VCC
VCC
−12
−24
−24
12
24
24
8
0
0
MAX
6
SN74AC74
MIN
2
2.1
3.15
3.85
0.9
1.35
1.65
VCC
VCC
−12
−24
−24
12
24
24
8
ns/V
mA
mA
V
V
V
V
MAX
6
UNIT
V
High-level input voltage
High-level output current
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
POST OFFICE BOX 655303
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3
SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003
SN54AC74, SN74AC74
DUAL POSITIVE EDGE TRIGGERED D TYPE FLIP FLOPS
WITH CLEAR AND PRESET
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
3V
IOH = −50
µA
IOH = −12 mA
IOH = −24 mA
IOH = −50 mA†
IOH = −75 mA†
IOL = 50
µA
IOL = 12 mA
IOL = 24 mA
IOL = 50 mA†
IOL = 75 mA†
Data pins
II
ICC
Ci
Control pins
VI = VCC or GND
VI = VCC or GND,
VI = VCC or GND
IO = 0
5.5 V
5.5 V
5V
3
4.5 V
5.5 V
3V
4.5 V
5.5 V
5.5 V
5.5 V
3V
4.5 V
5.5 V
3V
4.5 V
5.5 V
5.5 V
5.5 V
±0.1
±0.1
2
±1
±1
40
VOL
0.002
0.001
0.001
0.1
0.1
0.1
0.36
0.36
0.36
0.1
0.1
0.1
0.5
0.5
0.5
1.65
1.65
±1
±1
20
A
µA
µA
pF
VOH
TA = 25°C
MIN
TYP
MAX
2.9
4.4
5.4
2.56
3.86
4.86
4.49
5.49
5.49
SN54AC74
MIN
2.9
4.4
5.4
2.4
3.7
4.7
3.85
3.85
0.1
0.1
0.1
0.44
0.44
0.44
V
MAX
SN74AC74
MIN
2.9
4.4
5.4
2.46
3.76
4.76
V
MAX
UNIT
† Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
timing requirements over recommended operating free-air temperature range,
V
CC
= 3.3 V
"
0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
fclock
tw
tsu
th
Clock frequency
PRE or CLR low
Pulse duration
Setup time, data before CLK↑
Hold time, data after CLK↑
CLK
Data
PRE or CLR inactive
5.5
5.5
4
0
0.5
100
8
8
5
0.5
0.5
SN54AC74
MIN
MAX
70
7
7
4.5
0
0.5
ns
ns
ns
SN74AC74
MIN
MAX
95
UNIT
MHz
4
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DALLAS, TEXAS 75265
SN54AC74, SN74AC74
DUAL POSITIVE EDGE TRIGGERED D TYPE FLIP FLOPS
WITH CLEAR AND PRESET
SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003
timing requirements over recommended operating free-air temperature range,
V
CC
= 5 V"0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
fclock
tw
tsu
th
Clock frequency
PRE or CLR low
Pulse duration
Setup time, data before CLK↑
Hold time, data after CLK↑
CLK
Data
PRE or CLR inactive
4.5
4.5
3
0
0.5
140
5.5
5.5
4
0.5
0.5
SN54AC74
MIN
MAX
95
5
5
3
0
0.5
ns
ns
ns
SN74AC74
MIN
MAX
125
UNIT
MHz
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
"
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
MIN
TYP
MAX
100
3.5
PRE or CLR
CLK
Q or Q
Q or Q
4
4.5
3.5
125
8
10.5
8
8
12
12
13.5
14
SN54AC74
MIN
70
1
1
1
1
13
14
17.5
13.5
MAX
SN74AC74
MIN
95
2.5
3.5
4
3.5
13
13.5
16
14.5
ns
ns
MAX
UNIT
MHz
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
"
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
MIN
TYP
MAX
140
2.5
PRE or CLR
CLK
Q or Q
Q or Q
3
3.5
2.5
160
6
8
6
6
9
9.5
10
10
SN54AC74
MIN
95
1
1
1
1
9.5
10.5
12
10
MAX
SN74AC74
MIN
125
2
2.5
3
2.5
10
10.5
10.5
10.5
ns
ns
MAX
UNIT
MHz
operating characteristics, V
CC
= 3.3 V, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
f = 1 MHz
TYP
45
UNIT
pF
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