NT128D64SH4B0GM / NT128D64SH4BBGM
128MB : 16M x 64
PC3200 / PC2700 / PC2100 Unbuffered DDR SO-DIMM
200 pin Unbuffered DDR SO-DIMM
Based on DDR400/333/266 16Mx16 SDRAM
Features
• 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM)
• 16Mx64 Double Unbuffered DDR SO-DIMM based on 16Mx16
DDR SDRAM.
• Performance:
PC3200 PC2700 PC2100
Speed Sort
DIMM
CAS
Latency
f
CK
t
CK
Clock Frequency
Clock Cycle
-5/-5T
3
200
5
400
-6K
2.5
166
6
333
-75B
2.5
133
7.5
266
MHz
ns
MHz
Unit
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM
CAS
Latency: 2, 2.5, 3
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 13/9/1 Addressing (row/column/bank)
• 7.8
µs
Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 66-pin TSOP Type II Package
f
DQ
DQ Burst Frequency
• Intended for 133, 166 and 200 MHz applications
• Inputs and outputs are SSTL-2 compatible
• V
DD
= V
DDQ
= 2.5V ± 0.2V (2.6V ± 0.1V for DDR400A/B)
• SDRAMs have 4 internal banks for concurrent operation
• Module has one physical bank
• Differential clock inputs
Description
NT128D64SH4BBGM is an unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Small Outline Dual In-Line Memory Module
(SO-DIMM), organized as a single bank of 16Mx64 high-speed memory array. The module uses four 16Mx16 DDR SDRAMs in 400 mil
TSOP II packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of
these common design files minimizes electrical variation between suppliers. All NANYA DDR SDRAM DIMMs provide a high-performance,
flexible 8-byte interface in a 2.66” long space-saving footprint.
The DIMM is intended for use in applications operating up to 200 MHz clock speeds and achieves high-speed data transfer rates of up to
400 MHz. Prior to any access operation, the device
CAS
latency and burst type/ length/operation type must be programmed into the DIMM
by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of serial PD
data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
Ordering Information
Part Number
Speed
200MHz (5ns @ CL = 3)
NT128D64SH4BBGM-5
DDR400A
PC3200A 166MHz (6ns @ CL = 2.5)
133MHz (7.5ns @ CL = 2)
NT128D64SH4BBGM-5T
DDR400B
PC3200B
200MHz (5ns @ CL = 3)
166MHz (6ns @ CL = 2.5)
166MHz (6ns @ CL = 2.5)
133MHz (7.5ns @ CL = 2)
133MHz (7.5ns @ CL = 2.5)
100MHz (10ns @ CL = 2)
2.5V
16Mx64
Gold
2.6V
Power
Organization
Leads
NT128D64SH4BBGM-6K
NT128D64SH4BBGM-75B
NT128D64SH4B0GM-75B
DDR333
PC2700
DDR266B
PC2100
REV 1.0
12/11/2003
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT128D64SH4B0GM / NT128D64SH4BBGM
128MB : 16M x 64
PC3200 / PC2700 / PC2100 Unbuffered DDR SO-DIMM
Pin Description
CK0, CK1, CK2,
CK0, CK1, CK2
CKE0, CKE1
RAS
CAS
WE
S0, S1
A0-A9, A11, A12
A10/AP
BA0, BA1
V
REF
V
DDID
Differential Clock Inputs.
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Auto-precharge
SDRAM Bank Address Inputs
Ref. Voltage for SSTL_2 inputs
V
DD
Identification flag.
DQ0-DQ63
DQS0-DQS7
DM0-DM7
V
DD
V
DDQ
V
SS
NC
SCL
SDA
SA0-2
V
DDSPD
Data input/output
Bidirectional data strobes
Input Data Mask
Power
Supply voltage for DQs
Ground
No Connect
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Serial Presence Detect Address Inputs
Serial EEPROM positive power supply
Pinout
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Front
V
REF
V
SS
DQ0
DQ1
V
DD
DQS0
DQ2
V
SS
DQ3
DQ8
V
DD
DQ9
DQS1
V
SS
DQ10
DQ11
V
DD
CK0
CK0
V
SS
DQ16
DQ17
V
DD
DQS2
DQ18
Pin Back
2
4
6
8
V
REF
V
SS
DQ4
DQ5
Pin Front
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
V
SS
DQ19
DQ24
V
DD
DQ25
DQS3
V
SS
DQ26
DQ27
V
DD
NC
NC
V
SS
DQS8
NC
V
DD
NC
DU
V
SS
CK2
CK2
V
DD
CKE1
DU
A12
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Back
V
SS
DQ23
DQ28
V
DD
DQ29
DM3
V
SS
DQ30
DQ31
V
DD
NC
NC
V
SS
NC
NC
V
DD
NC
DU
V
SS
V
SS
V
DD
V
DD
CKE0
DU
Pin
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
Front
A9
V
SS
A7
A5
A3
A1
V
DD
A10/AP
BA0
WE
S0
DU
V
SS
DQ32
DQ33
V
DD
DQS4
DQ34
V
SS
DQ35
DQ40
V
DD
DQ41
DQS5
V
SS
Pin
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
Back
A8
V
SS
A6
A4
A2
A0
V
DD
BA1
RAS
CAS
S1
DU
V
SS
DQ36
DQ37
V
DD
DM4
DQ38
V
SS
DQ39
DQ44
V
DD
DQ45
DM5
V
SS
Pin Front
151 DQ42
153 DQ43
155 V
DD
157 V
DD
159 V
SS
161 V
SS
163 DQ48
165 DQ49
167 V
DD
169 DQS6
171 DQ50
173 V
SS
175 DQ51
177 DQ56
179 V
DD
181 DQ57
183 DQS7
185 V
SS
187 DQ58
189 DQ59
191 V
DD
193 SDA
195 SCL
197 V
DDSPD
199 V
DDID
Pin Back
152 DQ46
154 DQ47
156 V
DD
158
CK1
160 CK1
162 V
SS
164 DQ52
166 DQ53
168 V
DD
170 DM6
172 DQ54
174 V
SS
176 DQ55
178 DQ60
180 V
DD
182 DQ61
184 DM7
186 V
SS
188 DQ62
190 DQ63
192 V
DD
194 SA0
196 SA1
198 SA2
200 DU
10 V
DD
12 DM0
14 DQ6
16 V
SS
18 DQ7
20 DQ12
22 V
DD
24 DQ13
26 DM1
28 V
SS
30 DQ14
32 DQ15
34 V
DD
36 V
DD
38 V
SS
40 V
SS
42 DQ20
44 DQ21
46 V
DD
48 DM2
50 DQ22
100 A11
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
REV 1.0
12/11/2003
2
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT128D64SH4B0GM / NT128D64SH4BBGM
128MB : 16M x 64
PC3200 / PC2700 / PC2100 Unbuffered DDR SO-DIMM
Input/Output Functional Description
Symbol
CK0, CK1, CK2,
CK0, CK1, CK2
CKE0, CKE1
Type
(SSTL)
Polarity
Cross
point
Active
High
Function
The system clock inputs. All address and command lines are sampled on the cross point of
the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven
from the clock inputs and output timing for read operations is synchronized to the input
clock.
Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low.
By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh
mode.
Enables the associated DDR SDRAM command decoder when low and disables the
S0, S1
(SSTL)
Active
Low
Active
Low
command decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is
selected by S1.
RAS, CAS, WE
V
REF
V
DDQ
BA0, BA1
(SSTL)
Supply
Supply
(SSTL)
-
When sampled at the positive rising edge of the clock,
RAS, CAS, WE
define the operation to
be executed by the SDRAM.
Reference voltage for SSTL-2 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
A0 - A9
A10/AP
A11, A12
when sampled at the rising clock edge. In addition to the column address, AP is used to
(SSTL)
-
invoke auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high,
auto-precharge is selected and BA0/BA1 defines the bank to be precharged. If AP is low,
auto-precharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
DQ0 - DQ63
DQS0 - DQS7
(SSTL)
(SSTL)
-
Active
High
Active
High
Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.
Data strobes: Output with read data, input with write data. Edge aligned with read data,
centered on write data. Used to capture write data.
The data write masks, associated with one data byte. In Write mode, DM operates as a byte
mask by allowing input data to be written if it is low but blocks the write operation if it is high.
In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is
not used on x64 modules.
Power and ground for the DDR SDRAM input buffers and core logic
Address inputs. Connected to either V
DD
or V
SS
on the system board to configure the Serial
Presence Detect EEPROM address.
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V DD to act as a pull-up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V DD to act as a pull-up.
Serial EEPROM positive power supply.
(SSTL)
DM0 - DM7
V
DD
, V
SS
SA0 – SA2
SDA
SCL
V
DDSPD
Input
Supply
-
-
-
Supply
REV 1.0
12/11/2003
3
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT128D64SH4B0GM / NT128D64SH4BBGM
128MB : 16M x 64
PC3200 / PC2700 / PC2100 Unbuffered DDR SO-DIMM
Functional Block Diagram
(1 Bank, 16Mx16 DDR SDRAMs)
S0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
D0
CS
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
D2
CS
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
CS
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
CS
D1
D3
BA0-BA1
A0-A12
RAS
CAS
CKE0
CKE1
WE
Notes :
1.
2.
3.
4.
BA0-BA1 : SDRAMs D0-D3
A0-A12 : SDRAMs D0-D3
RAS
: SDRAMs D0-D3
CAS
: SDRAMs D0-D3
CKE : SDRAMs D0-D3
N.C.
WE
: SDRAMs D0-D3
SCL
WP
V
DDSPD
V
DD
/V
DDQ
V
REF
V
SS
V
DDID
Serial PD
A0
SA0
A1
SA1
A2
SA2
SPD
D0-D3
D0-D3
D0-D3
CK0
CK0
CK1
CK1
CK2
SDA
CK2
2 loads
2 loads
0 loads
DQ wiring may differ from that described in this drawing.
DQ/DQS/DM/CKE/S relationships are maintained as shown.
DQ/DQS/DM/DQS resistors are 22+/- 5% Ohms.
V
DDID
strap connections (for memory device V
DD
, V
DDQ
):
STRAP OUT (OPEN): V
DD
= V
DDQ
STRAP IN (V
SS
): V
DD
is not equal to V
DDQ
.
REV 1.0
12/11/2003
4
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT128D64SH4B0GM / NT128D64SH4BBGM
128MB : 16M x 64
PC3200 / PC2700 / PC2100 Unbuffered DDR SO-DIMM
Serial Presence Detect
(Part 1 of 2)
Byte
0
1
2
3
4
5
6
7
8
Description
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Bank
Data Width of Assembly
Data Width of Assembly (cont’)
Voltage Interface Level of this Assembly
DDR SDRAM Device Cycle Time
9
DDR266B/333, CL=2.5
DDR400A/B, CL=3
DDR SDRAM Device Access Time from Clock
10
DDR266B/333, CL=2.5
DDR400A/B, CL=3
11
12
13
14
15
16
17
DIMM Configuration Type
Refresh Rate/Type
Primary DDR SDRAM Width
Error Checking DDR SDRAM Device Width
DDR SDRAM Device Attr: Min CLK Delay, Random Col Access
DDR SDRAM Device Attributes: Burst Length Supported
DDR SDRAM Device Attributes: Number of Device Banks
DDR266B
18
DDR SDRAM Device Attributes:
CAS Latencies Supported
DDR SDRAM Device Attributes: CS Latency
DDR SDRAM Device Attributes: WE Latency
DDR SDRAM Device Attributes:
DDR SDRAM Device Attributes: General
DDR266B/333
DDR400A/B
DDR266B
23
Minimum Clock Cycle at CL=2.5
DDR333
DDR400A
DDR400B
Maximum Data Access Time from Clock at
24
CL=2 (DDR266B/DDR333)
CL=2.5 (DDR400A/DDR400B)
DDR266B
DDR333
DDR400A
DDR400B
DDR266B
25
Minimum Clock Cycle Time at CL=1
DDR333
DDR400A
DDR400B
DDR266B
26
Maximum Data Access Time from Clock at CL=1
DDR333
DDR400A
DDR400B
DDR333
DDR400A
DDR400B
19
20
21
22
DDR266B
DDR333
DDR400A
DDR400B
DDR266B
DDR333
DDR400A
DDR400B
SPD Entry Value
128
256
SDRAM DDR
13
9
1
x64
x64
SSTL 2.5V
7.5ns
6.0ns
5.0ns
0.75ns
0.70ns
0.60ns
Non-Parity
SR/1x(7.8us)
x16
N/A
1 Clock
2,4,8
4
2/2.5
2/2.5
2/2.5/3
2.5/3
0
1
Differential Clock
±0.2V Tolerance
±0.1V Tolerance
7.5ns
10ns
5.0ns
6.0ns
0.70ns
0.75ns
0.60ns
0.70ns
N/A
N/A
N/A
7.5ns
N/A
N/A
N/A
7.5ns
Serial PD Data Entry
(Hexadecimal)
80
08
07
0D
09
01
40
00
04
75
60
50
75
70
60
00
82
10
00
01
0E
04
0C
0C
1C
18
01
02
20
00
75
A0
50
60
70
75
60
70
00
00
00
75
00
00
00
75
Note
REV 1.0
12/11/2003
5
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
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