74LCX646
LOW VOLT. CMOS OCTAL BUS TRANSCEIVER/REGISTER
WITH 5 VOLT TOLERANT INPUTS AND OUTPUTS(3-STATE)
s
s
s
s
s
s
s
s
s
s
5V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED:
t
PD
= 7.0 ns (MAX.) at V
CC
= 3V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 646
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
DESCRIPTION
The 74LCX646 is a low voltage CMOS OCTAL
BUS
TRANSCEIVER
AND
REGISTER
(3-STATE) fabricated with sub-micron silicon gate
and double-layer metal wiring C
2
MOS technology.
It is ideal for low power and high speed 3.3V
applications; it can be interfaced to 5V signal
environment for both inputs and outputs.
Figure 1: Pin Connection And IEC Logic Symbols
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This device consists of bus transceiver circuits
with 3 state, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data
directly from the input bus or from the internal
registers. Data on the A or B bus will be clocked
into register on the low to high transition of the
appropriate clock pin (Clock AB or Clock BA).
Enable (G) and direction (DIR) pins are provided
to control the transceiver functions. In the
transceiver mode, data present at the
high-impedance port may be stored in either
register or in both. The select controls (Select AB
select BA) can multiplex stored and real time
(transparent mode) data. The direction control
determines which bus will receive data when
enable G is active (low). In the isolation mode
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M74LCX646
(enable G high), "A" data may be stored in one
register and/or "B" data may be stored in the other
register. When an output function is disabled, the
input function is still enabled and may be used to
store and transmit data. Only one of the two
buses, A or B, may be driven at a time. It has
same speed performance at 3.3V than 5V
Figure 2: Input And Output Equivalent Circuit
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Table 2: Pin Description
PIN N°
1
2
3
4, 5, 6, 7, 8, 9, 10, 11
20, 19, 18, 17, 16, 15, 14, 13
21
22
23
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CLOCK AB (CAB)
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SYMBOL
NAME AND FUNCTION
A to B Clock Input (LOW to HIGH,
Edge-Triggered)
Select A to B Source Input
Direction Control Input
A Data Inputs/Outputs
B Data Inputs/Outputs
Output Enable Input (Active LOW)
Select B to A Source Input
B to A Clock Input (LOW to HIGH,
Edge Triggered)
Ground (0V)
Positive Supply Voltage
SELECT AB (SAB)
DIR
A1 to A8
B1 to B8
G
SELECT BA (SBA)
CLOCK BA (CBA)
GND
V
CC
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M74LCX646
Table 3: Truth Table
G
DIR CAB CBA SAB SBA
X
H
X
X
X
X
X
X
A
INPUTS
Z
B
INPUTS
Z
FUNCTION
X
X*
X*
L
L
H
H
X
X
X
X
L
H
X
X*
X*
X*
X*
L
L
X*
X*
X
X
X
L
L
H
H
X
X
X
Both the A bus and the B bus are inputs
The Output functions of the A and B bus are disabled
Both the A and B bus are used as inputs to the internal
INPUTS
INPUTS flip-flops. Data at the bus will be stored on low to high
transition of the clock inputs.
INPUTS OUTPUTS The A bus are inputs and the B bus are outputs
L
L
The data at the A bus are displayed at the B bus
H
H
L
L
The data at the A bus are displayed at the B bus. The
data of the A bus are stored to internal flip-flop on low
H
H
to high transition of the clock pulse
The data stored to the internal flip-flop are displayed at
X
Qn
the B bus.
L
L
The data at the A bus are stored to the internal flip-flop
on low to high transition of the clock pulse. The states
H
H
of the internal flip-flops output directly to the B bus.
OUTPUTS INPUTS The B bus are inputs and the A bus are outputs.
L
L
The data at the B bus are displayed at the A bus
H
H
L
L
The data at the B bus are displayed at the A bus. The
data of the B bus are stored to the internal flip-flop on
H
H
low to high transition of the clock pulse.
The data stored to the internal flip-flops are displayed
Qn
X
at the A bus
L
L
The data at the B bus are stored to the internal flip-flop
on low to high transition of the clock pulse. The states
H
H
of the internal flip-flops output directly to the A bus.
X : Don’t Care
Z : High Impedance
Qn: The data stored to the internal flip-flops by most recent low to high transition of the clock inputs
* : The data at the A and B bus will be stored to the internal flip-flops on every low to high transition of the clock inputs.
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M74LCX646
Figure 3: Logic Diagram
This logic diagram has not be used to estimate propagation delays
Figure 4: Timing Chart
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M74LCX646
Table 4: Absolute Maximum Ratings
Symbol
V
CC
V
I
V
O
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage (OFF State)
DC Output Voltage (High or Low State) (note 1)
DC Input Diode Current
DC Output Diode Current (note 2)
DC Output Current
DC Supply Current per Supply Pin
DC Ground Current per Supply Pin
Storage Temperature
Lead Temperature (10 sec)
Parameter
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to +7.0
-0.5 to V
CC
+ 0.5
- 50
- 50
±
50
±
100
±
100
-65 to +150
300
Unit
V
V
V
V
mA
mA
mA
mA
mA
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) I
O
absolute maximum rating must be observed
2) V
O
< GND
Table 5: Recommended Operating Conditions
Symbol
V
CC
V
I
V
O
V
O
I
OH
, I
OL
I
OH
, I
OL
T
op
dt/dv
Supply Voltage (note 1)
Input Voltage
Output Voltage (OFF State)
Output Voltage (High or Low State)
Parameter
High or Low Level Output Current (V
CC
= 3.0 to 3.6V)
High or Low Level Output Current (V
CC
= 2.7V)
Operating Temperature
Input Rise and Fall Time (note 2)
1) Truth Table guaranteed: 1.5V to 3.6V
2) V
IN
from 0.8V to 2V at V
CC
= 3.0V
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°C
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Value
Unit
V
V
V
V
mA
mA
°C
ns/V
2.0 to 3.6
0 to 5.5
0 to 5.5
0 to V
CC
±
24
±
12
-55 to 125
0 to 10
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