Datasheet> 器件分类 > 嵌入式处理器和控制器> 微控制器和处理器> SII3124ACBHU

文档预览

SII3124ACBHU: 产品描述PCI Bus Controller, CMOS, PBGA364, 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小592KB，共88页; 制造商Silicon image; 官网地址http://www.siliconimage.com/; 标准

下载文档详细参数选型对比全文预览文档解析

SII3124ACBHU概述

PCI Bus Controller, CMOS, PBGA364, 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364

SII3124ACBHU规格参数

参数名称	属性值
是否无铅	不含铅
是否Rohs认证	符合
厂商名称	Silicon image
零件包装代码	BGA
包装说明	BGA, BGA364,20X20,40
针数	364
Reach Compliance Code	compliant
ECCN代码	EAR99
地址总线宽度
总线兼容性	PCI
最大时钟频率	133 MHz
最大数据传输速率	300 MBps
外部数据总线宽度	64
JESD-30 代码	S-PBGA-B364
长度	21 mm
端子数量	364
最高工作温度	70 °C
最低工作温度
封装主体材料	PLASTIC/EPOXY
封装代码	BGA
封装等效代码	BGA364,20X20,40
封装形状	SQUARE
封装形式	GRID ARRAY
峰值回流温度（摄氏度）	NOT SPECIFIED
电源	1.8,3.3 V
认证状态	Not Qualified
座面最大高度	1.8 mm
最大供电电压	3.6 V
最小供电电压	3 V
标称供电电压	3.3 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	21 mm
uPs/uCs/外围集成电路类型	BUS CONTROLLER, PCI

文档解析

SiI3124A的核心是Serial ATA II兼容性，支持3.0 Gb/s传输速率和Port Multiplier功能，实现单端口多设备连接。其PHY层集成参考时钟输入（XTALI/CLKI），支持25 MHz或100 MHz外部时钟，Jitter要求小于50 ps RMS。Link层处理FIS（Frame Information Structure）协议，包括Host to Device和Device to Host FIS交换，并支持软复位序列生成。特性包括Plesiochronous单PLL架构，一个PLL服务四端口，减少组件数量。技术亮点包括对Native Command Queuing（NCQ）的全面支持，允许31个命令槽位并行处理，每个槽位128字节LRAM（Local RAM）存储PRB和SGT。PRB结构可定义为标准ATA命令、PACKET命令（用于ATAPI）、软复位或外部命令类型，通过控制字段（Control Field）和协议覆盖字段（Protocol Override Field）灵活配置。数据传输机制利用SGE定义连续内存区域，支持TRM（终止）、LNK（链接）、DRD（丢弃数据）和XCF（外部命令获取）标志，优化数据流管理。错误恢复流程包括自动重试和状态寄存器报告，如SError寄存器诊断位。控制器适用于高性能存储应用，如SAN和NAS系统。其低延迟设计通过PCI-X突发和DMA控制器实现，减少CPU干预。封装引脚包括REXT用于终端校准，LED输出用于活动指示，支持多主I2C接口用于外部设备通信。电源噪声要求严格，如1.8V模拟电源噪声小于50 mV，确保信号完整性。SiI3124A的编程模型基于端口逻辑块，每个端口包含命令获取状态机、命令执行状态机和数据路径DMA控制器。LRAM（512x64双端口）存储命令槽位，每个槽位容纳64字节PRB和64字节SGT。命令发布支持两种方法：直接方法（主机通过Base Address 1映射写入LRAM）和间接方法（SiI3124通过PCI-X主控读取PRB）。执行流程包括FIS传输、数据DMA（主机内存与SATA设备间）和完成中断报告，Slot Status寄存器记录命令状态。寄存器空间分为三部分：Base Address 0（全局寄存器如Global Control和Interrupt Status）、Base Address 1（端口特定寄存器如Port LRAM和Port Control）和Base Address 2（全局/端口寄存器访问接口）。中断系统共享四个PCI中断信号（INTA#至INTD#），通过Port Interrupt Enable寄存器配置源映射。Auto-Initialization特性允许从Flash或EEPROM加载配置，时序参数如Flash访问时间符合标准规范。电源管理支持PCI Power Management Capability，包括D0-D3状态切换。应用优势体现在高效队列管理，支持LCQ和NCQ，兼容非零偏移和乱序交付。错误处理包括Command Error寄存器记录错误代码（如FIS超时或CRC错误），并通过BIST控制寄存器执行环回测试。物理设计优化信号完整性，如SATA接口差分阻抗100Ω±15%，满足眼图规范。适用于需要高可靠性的环境，如工业存储控制器。

SII3124ACBHU文档预览

Data Sheet

SiI3124A PCI-X to Serial ATA Controller

Data Sheet

Document # SiI-DS-0160-C

PCI-X to Serial ATA Controller

Data Sheet

Silicon Image, Inc.

October 2006

Revision History

Revision

Comment

Date

04/10/06

10/10/06

2/02/07

Derived from SiI3124-2 Datasheet Rev B

Correct inconsistence sentence

This Document is no longer under NDA. Removed confidential markings

SiI-DS-0160-C

PCI-X to Serial ATA Controller

Data Sheet

Silicon Image, Inc.

Table of Contents

Overview ...........................................................................................................................................8

1.1

1.1.1

1.1.2

1.1.3

Features ..................................................................................................................................................... 8

Overall Features ...................................................................................................................................................8

PCI-X Features.....................................................................................................................................................8

Serial ATA Features .............................................................................................................................................8

1.2

References ................................................................................................................................................. 8

Device Electrical Characteristics ............................................................................................................ 9

SATA Interface Timing Specifications .................................................................................................. 11

SATA Interface Transmitter Output Jitter Characteristics.................................................................. 11

CLKI SerDes Reference Clock Input Requirements ............................................................................ 12

Power Supply Noise Requirements ...................................................................................................... 12

PCI 33 MHz Timing Specifications ........................................................................................................ 12

PCI 66 MHz Timing Specifications ........................................................................................................ 13

PCI-X 133 MHz Timing Specifications................................................................................................... 13

SiI3124A Pin Listing................................................................................................................................ 14

SiI3124A Ball Mapping............................................................................................................................ 18

SiI3124A Pin Descriptions...................................................................................................................... 19

PCI(X) Pins.........................................................................................................................................................19

Flash / I

C Pins...................................................................................................................................................20

Serial ATA Signals..............................................................................................................................................20

Test Pins ............................................................................................................................................................21

NC Pins ..............................................................................................................................................................21

Power/Ground Pins ............................................................................................................................................22

Electrical Characteristics ................................................................................................................9

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

Pin Definition ..................................................................................................................................14

3.1

3.2

3.3

3.3.1

3.3.2

3.3.3

3.3.4

3.3.5

3.3.6

Package Drawing............................................................................................................................23

Programming Model.......................................................................................................................25

5.1

5.2

5.3

SiI3124A Block Diagram ......................................................................................................................... 25

SiI3124A S-ATA Port Block Diagram..................................................................................................... 26

Data Structures ....................................................................................................................................... 27

The Command Slot.............................................................................................................................................27

The Scatter/Gather Entry (SGE).........................................................................................................................28

The Scatter/Gather Table (SGT) ........................................................................................................................29

The Port Request Block (PRB)...........................................................................................................................29

The PRB Control Field........................................................................................................................................31

The PRB Protocol Override Field .......................................................................................................................32

Standard ATA Command PRB Structure............................................................................................................33

PACKET Command PRB Structure....................................................................................................................35

Soft Reset PRB Structure...................................................................................................................................36

External Command PRB Structure .....................................................................................................................37

Interlocked Receive PRB Structure ....................................................................................................................38

Command Issuance............................................................................................................................................39

Reset and Initialization .......................................................................................................................................39

Port Ready .........................................................................................................................................................40

Port Reset Operation..........................................................................................................................................40

Initialization Sequence........................................................................................................................................40

Interrupts and Command Completion.................................................................................................................41

Interrupt Sources ................................................................................................................................................41

Command Completion – The Slot Status Register .............................................................................................44

The Attention Bit .................................................................................................................................................45

Interrupt Service Procedure................................................................................................................................45

Interrupt No Clear on Read ................................................................................................................................45

Error Processing.................................................................................................................................................45

SiI-DS-0160-C

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

5.3.9

5.3.10

5.3.11

5.4

Operation ................................................................................................................................................. 39

5.4.1

5.4.2

5.4.3

5.4.4

5.4.5

5.4.6

5.4.7

5.4.8

5.4.9

5.4.10

5.4.11

5.4.12

PCI-X to Serial ATA Controller

Data Sheet

Silicon Image, Inc.

5.4.13

Error recovery procedures..................................................................................................................................46

Auto-Initialization ...........................................................................................................................48

6.1

6.2

Auto-Initialization from Flash................................................................................................................. 48

Auto-Initialization from EEPROM .......................................................................................................... 49

PCI Configuration Space ........................................................................................................................ 50

Device ID – Vendor ID........................................................................................................................................51

PCI Status – PCI Command...............................................................................................................................51

PCI Class Code – Revision ID............................................................................................................................52

BIST – Header Type – Latency Timer – Cache Line Size ..................................................................................53

Base Address Register 0....................................................................................................................................53

Base Address Register 1....................................................................................................................................54

Base Address Register 2....................................................................................................................................54

Subsystem ID – Subsystem Vendor ID ..............................................................................................................55

Expansion ROM Base Address ..........................................................................................................................55

Capabilities Pointer.............................................................................................................................................56

Max Latency – Min Grant – Interrupt Pin – Interrupt Line ...................................................................................56

PCI-X Capability .................................................................................................................................................57

PCI-X Status.......................................................................................................................................................57

Header Write Enable ..........................................................................................................................................58

MSI Capability ....................................................................................................................................................58

Message Address...............................................................................................................................................58

MSI Message Data .............................................................................................................................................59

Power Management Capability...........................................................................................................................59

Power Management Control + Status.................................................................................................................59

Port Slot Status Registers ..................................................................................................................................61

Global Control ....................................................................................................................................................61

Global Interrupt Status........................................................................................................................................62

PHY Configuration..............................................................................................................................................63

BIST Control Register.........................................................................................................................................63

BIST Pattern Register.........................................................................................................................................63

BIST Status Register ..........................................................................................................................................64

Flash Address ....................................................................................................................................................64

Flash Memory Data / GPIO Control....................................................................................................................65

C Address ........................................................................................................................................................65

C Data / Control ...............................................................................................................................................66

Port LRAM..........................................................................................................................................................68

Port Slot Status ..................................................................................................................................................68

Port Control Set ..................................................................................................................................................69

Port Status..........................................................................................................................................................70

Port Control Clear...............................................................................................................................................70

Port Interrupt Status ...........................................................................................................................................70

Port Interrupt Enable Set / Port Interrupt Enable Clear.......................................................................................72

32-bit Activation Upper Address .........................................................................................................................72

Port Command Execution FIFO .........................................................................................................................72

Port Command Error ..........................................................................................................................................73

Port FIS Configuration ........................................................................................................................................75

Port PCI(X) Request FIFO Threshold.................................................................................................................76

Port 8B/10B Decode Error Counter ....................................................................................................................76

Port CRC Error Counter .....................................................................................................................................77

Port Handshake Error Counter ...........................................................................................................................77

Port PHY Configuration ......................................................................................................................................78

Port Device Status Register ...............................................................................................................................78

Port Device QActive Register .............................................................................................................................79

Port Context Register .........................................................................................................................................79

SControl .............................................................................................................................................................80

SStatus...............................................................................................................................................................81

SError .................................................................................................................................................................82

SActive ...............................................................................................................................................................82

SiI-DS-0160-C

Register Definitions .......................................................................................................................50

7.1

7.1.1

7.1.2

7.1.3

7.1.4

7.1.5

7.1.6

7.1.7

7.1.8

7.1.9

7.1.10

7.1.11

7.1.12

7.1.13

7.1.14

7.1.15

7.1.16

7.1.17

7.1.18

7.1.19

7.2

Internal Register Space – Base Address 0 ........................................................................................... 60

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

7.2.6

7.2.7

7.2.8

7.2.9

7.2.10

7.2.11

7.3

Internal Register Space – Base Address 1 ........................................................................................... 67

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.3.6

7.3.7

7.3.8

7.3.9

7.3.10

7.3.11

7.3.12

7.3.13

7.3.14

7.3.15

7.3.16

7.3.17

7.3.18

7.3.19

7.3.20

7.3.21

7.3.22

7.3.23

PCI-X to Serial ATA Controller

Data Sheet

Silicon Image, Inc.

7.4

7.4.1

7.4.2

7.4.3

7.4.4

Internal Register Space – Base Address 2 ........................................................................................... 83

Global Register Offset ........................................................................................................................................83

Global Register Data ..........................................................................................................................................83

Port Register Offset ............................................................................................................................................83

Port Register Data ..............................................................................................................................................83

Power Management........................................................................................................................84

Flash, GPIO, EEPROM, and I

C Programming.............................................................................85

9.1

9.1.1

9.1.2

Flash Memory Access ............................................................................................................................ 85

C Operation ........................................................................................................................................... 86

PCI Direct Access...............................................................................................................................................85

Register Access .................................................................................................................................................85

9.2

SiI-DS-0160-C

查看更多（仅显示前5页内容，查看全部内容请下载文档。）>

SII3124ACBHU相似产品对比

	SII3124ACBHU
描述	PCI Bus Controller, CMOS, PBGA364, 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364
是否无铅	不含铅
是否Rohs认证	符合
厂商名称	Silicon image
零件包装代码	BGA
包装说明	BGA, BGA364,20X20,40
针数	364
Reach Compliance Code	compliant
ECCN代码	EAR99
总线兼容性	PCI
最大时钟频率	133 MHz
最大数据传输速率	300 MBps
外部数据总线宽度	64
JESD-30 代码	S-PBGA-B364
长度	21 mm
端子数量	364
最高工作温度	70 °C
封装主体材料	PLASTIC/EPOXY
封装代码	BGA
封装等效代码	BGA364,20X20,40
封装形状	SQUARE
封装形式	GRID ARRAY
峰值回流温度（摄氏度）	NOT SPECIFIED
电源	1.8,3.3 V
认证状态	Not Qualified
座面最大高度	1.8 mm
最大供电电压	3.6 V
最小供电电压	3 V
标称供电电压	3.3 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	21 mm
uPs/uCs/外围集成电路类型	BUS CONTROLLER, PCI

SII3124ACBHU

SII3124ACBHU概述

SII3124ACBHU规格参数

文档解析

SII3124ACBHU文档预览

SII3124ACBHU相似产品对比

推荐资源